sim> show version
VAX 11/780 simulator V4.0-0 Current        git commit id: 89cd649c
sim> show version
VAX 11/780 simulator V4.0-0 Current
    Simulator Framework Capabilities:
        64b data
        64b addresses
        Threaded Ethernet Packet transports:PCAP:TAP:VDE:NAT:UDP
        Idle/Throttling support is available
        Virtual Hard Disk (VHD) support
        Asynchronous I/O support (Lock free asynchronous event queue)
        Asynchronous Clock support
        FrontPanel API Version 12
    Host Platform:
        Compiler: GCC 4.2.1 Compatible FreeBSD Clang 8.0.1 (tags/RELEASE_801/final 366581)
        Simulator Compiled as C arch: x64 (Release Build) on Mar 19 2020 at 01:00:03
        Build Tool: simh-makefile
        Memory Access: Little Endian
        Memory Pointer Size: 64 bits
        Large File (>2GB) support
        SDL Video support: No Video Support
        PCRE RegEx (Version 8.43 2019-02-23) support for EXPECT commands
        OS clock resolution: 1ms
        Time taken by msleep(1): 19ms
        Ethernet packet info: libpcap version 1.9.0
        Time taken by msleep(1): 19ms
        OS: FreeBSD freebsd-simh-host.sanyalnet.lan 12.1-RELEASE-p2 FreeBSD 12.1-RELEASE-p2 GENERIC  amd64
        git commit id: 89cd649c
        git commit time: 2020-03-18T00:47:48-07:00
sim> show device
VAX 11/780 simulator configuration

CPU	idle disabled, model=VAX 11/780, Implementing: All standard VAX instructions and Compatibility mode
TLB	2 units
SBI
MCTL0	nexus=1, address=20002000
MCTL1	nexus=2, address=20004000
UBA	nexus=3, address=20006000, autoconfiguration enabled
MBA0	nexus=8, address=20010000
MBA1	nexus=9, address=20012000
TODR
TMR
TTI
TTO
CS
TC	disabled
TDC	disabled
DZ	address=2013E040-2013E05F*, vector=C0-DC*, BR5, lines=32
VH	disabled
CR	disabled
LPT	address=2013FF4C-2013FF4F, vector=80, BR4
RP	Massbus adapter 0, 8 units
RL	address=2013F900-2013F909, vector=70, BR5, 4 units
HK	address=2013FF20-2013FF3F, vector=88, BR5, 8 units
RK	disabled
RQ	address=2013F468-2013F46B, no vector, BR5, UDA50, 4 units
RQB	disabled
RQC	disabled
RQD	disabled
RY	address=2013FE78-2013FE7B, vector=B4, BR5, 2 units
TU	Massbus adapter 1, TM03, 8 units
TS	address=2013F550-2013F553, vector=94, BR5
TQ	TU81 (180MB), address=2013F940-2013F943, no vector, BR5, 4 units
XU	disabled
XUB	disabled
DMC	disabled
CH	disabled
sim> 
sim> 
sim> exit
Goodbye
