/*
 *
 */
 
/* HW registers */
/* PLX definitions */
#define PLX_INTCR   0x4c
/* DIO definitions */
#define DIO_PORTA       0x00
#define DIO_PORTB       0x01
#define DIO_PORTC       0x02
#define DIO_CONNCTRL    0x03
#define DIO_ISC         0x20
#define DIO_CLEARINT    0x30

#include <types.h>
#if !defined(_EDITMOD)
#include "dio7224.edm"
#endif

#if defined(REG_WIDTH)
#  if REG_WIDTH == 8
     typedef u_char reg_type_t;
#  else
#    error REG_WIDTH value not supported (only 8 supported)
#  endif
#else
typedef u_char reg_type_t;
#endif

/*
 * On using PCI we will only use the v_ports[0] entry for 
 * the base address for access. This address will be modified
 * as needed. We will leave v_port as is so IOMAN will not
 * see the address change as a issue on devices that are not
 * permently inized.
*/

#if !defined(_EDITMOD) /* No need to parse this info when building descriptor */

#include <pcicnfg.h>
#define PORTADDR v_ports[0]
#define ADLINK_PCI_VENDOR_ID 0x144A
#define ADLINK_PCI_DEVICE_ID 0x7248 

#if !defined(IRQ_BASE_OFFSET)
#define IRQ_BASE_OFFSET 0x40
#endif

#if !defined(PCI_IO_SPACE_BASE)
#define PCI_IO_SPACE_BASE 0x0
#endif

#if !defined(EV1_NAME)
#define EV1_NAME "LMS_H1"
#endif

#if !defined(EV2_NAME)
#define EV2_NAME "LMS_H2"
#endif

/* max no. of ports in case of 7296 */
#define NUMPORTS    4

#endif /* (_EDITMOD) */

#if		!defined(__STDC__) && !defined(_ANSI_EXT)
#ifndef volatile
#define	volatile
#endif
#endif