The fourth-generation processors are also particularly notable because they are designed to scale easily to faster versions of the CMOS technology. This fourth-generation family of processors includes several members, each sharing a common design, but each implemented with a different iteration of silicon technology. We can expect to see the performance for this 64-bit PowerPC processor range from about 250 MHz to about 800 MHz. Work also is underway in IBM’s Research division to get more than 1 gigahertz (GHz) out of this type of processor. So if IBM chooses, this third-generation design has the possibility to last well beyond Version 4.

Looking to a fifth generation of processors for the AS/400 provides some interesting speculation. Multiple options are available, and I want to look at a couple of them. But first, let’s look at what is happening to the CMOS technology. Sometime perhaps around the year 2005, we will have the capability to put 100 million transistors on a single chip. How all of those circuits will be used is a subject of much debate.

Today’s processor chips have from 5 million to 8 million circuits. One obvious use for the additional circuits is to increase on-chip cache sizes. Another use for the additional silicon real estate is to consolidate the functions now provided on separate chips. Still another use is to provide new functions on the chip, such as Intel is doing with its incorporation of the MMX technology into its Pentium family of processors. Even with all these new uses, we still may not be able to use all the additional circuits.

We could use the additional circuits to build bigger, wider processors. Processors that are 128, or even 256, bits wide are not unthinkable. Some special-purpose processors, such as the video processor many PCs use, are at 128 bits today. Of course, the problem with moving general-purpose processors to the larger sizes is the software. By 2005, many companies will just be getting to 64-bit software. To expect another adoption cycle of 12 years to get to 128- or 256-bit processors is probably not reasonable.

A more realistic design is to package multiple processors on a single chip. With the advances made in SMP designs, for example, we can reasonably expect to put an n-way SMP node with all its cache memories on a single chip. Such an implementation would not require changes to any existing system software that is already SMP enabled. As SMP designs scale upward, packaging multiple processors on a single chip will also let us make use of the 1 billion transistors on a chip that we expect to see sometime beyond the year 2010.

In fact, the fourth generation of AS/400 processors has already started down this path. Each processor in the fourth-generation family has two complete sets of registers on a single chip. The processor hardware can timeshare these sets of registers between two software threads of execution. As I described in Chapter 9, a process can have one or more executable entities, called threads. Threads represent a level of parallelism in a process, because multiple threads can be concurrently executing — which usually means having multiple processors executing multiple threads. However, a single processor with multiple sets of registers that can be timeshared by the hardware can also be used to process multiple threads. Such a design is called a multithreaded processor.

In Chapter 2, we saw how today’s processors incur many idle cycles waiting for cache misses and long memory-transfer times. Instead of wasting these idle cycles, a multithreaded processor can use them to execute instructions from another thread. Multithreading increases the processor utilization and thereby produces higher throughput. Late in the 1970s, the HEP (heterogeneous element processor) supercomputer from now-defunct Denelcor demonstrated that a multithreaded processor could support 16 instruction streams, or threads.

This idea of multithreaded processors fits the AS/400 design nicely. Currently, no single-processor AS/400 exists. Even the smallest systems have two processors: one main processor and one IOP. With all future IOPs moving to PowerPC, the AS/400 is nicely positioned to take advantage of multithreaded PowerPC processors in every system. For example, we can use one set of registers on a third-generation processor chip for a main processor, multithreaded with the other set of registers for an IOP. This could lead to lower-cost AS/400s that require the use of only one chip. Or, with the introduction of native threads in 1998, we could support multiple threads in a process on each processor chip.

As we expand beyond the fourth generation of processors and their multithreading capability, we can look at packaging multiple independent processors on a single chip. In an AS/400, we could certainly use the multiple processors as an SMP node on a chip, but there are other possibilities. Imagine for a moment that we could dynamically assign the processors on the chip to a specific function. At one instant, all the processors might be doing I/O operations; at the next instant all or many of them could be used for processing. The possibilities for future AS/400 designs are mind-boggling.

Beyond RISC

Whenever I talk about processor technologies beyond RISC, many people within IBM become very excited. IBM’s strategy for future processors in the AS/400e series and the RS/6000 is PowerPC. Other companies seem to be planning to abandon their current processor architectures. For example, Intel shows signs of moving away from the x86 architecture with it’s new IA-64 architecture. Although the details of this 64-bit architecture, which will first appear in the processor code named Merced, are not fully disclosed, it does look to be incompatible with x86. Only time will tell what this means for existing PC software. Still other processor vendors may not survive the dramatic increase in chip manufacturing costs that will occur around 2005.

In Chapter 2, I pointed out that the cost of a silicon foundry capable of manufacturing chips with transistors smaller than 0.1 micron will likely be $10 billion. This probably means that a vendor such as Digital, whose annual revenue is about equal to the foundry cost, will no longer make Alpha processors. And HP has already said it will stop making PA-RISC processors and instead will rely on joint designs with Intel. The press has also reported widely that HP may not even upgrade its HP-UX operating system to 64 bits, but instead will join forces with Santa Cruz Operations (SCO) to create a new 64-bit Unix operating system. SCO Unix today runs on Intel processors, giving more credibility to the possibility of HP moving exclusively to the IA-64 architecture. It will be interesting to watch HP 9000 customers try to move to new processor hardware and a new operating system without disrupting their businesses.