The AS/400 architecture also reduced the need for high-performance processors. In Chapters 8 and 9, we saw that both the AS/400’s single-level store and its highly efficient tasking structure eliminate the need to execute many instructions in the operating system that other computers must execute to run the same applications. Earlier in this chapter, we also saw that because of the AS/400’s persistent single-level store, the AS/400 executes fewer instructions and fewer disk accesses when it deals with objects. Not having to execute an instruction is equivalent to having an infinite-speed processor for that instruction.

Unlike interactive applications, most of the new applications being introduced on the AS/400 do stress the processor performance. Starting with the move to client/server computing in the early 1990s, AS/400 applications have become more compute intensive. As we discussed earlier, the server models were one way we could support more compute-intensive applications. The PowerPC technology was another.

The PowerPC technology drives the core of our performance improvements for Version 4. I described our move to the PowerPC technology in Chapter 2. I also described the generations of 64-bit processors that have been or are being developed in Rochester. We announced the first- and second-generation processors in 1994 and 1995 as the first PowerPC RISC processors in the AS/400. The third and fourth generation of PowerPC processors are part of Version 4.

Single-processor performance is important for PC systems, where the processor must handle all processing and I/O operations. Processors with high MHz ratings and large caches are necessary to achieve high performance in these systems. For multiuser systems, however, using multiple processors can result in far greater performance. When memory sharing is necessary, as it is for most commercial applications, an SMP model is the most efficient way to achieve high performance.

In Chapter 2, we saw that the bottleneck in most SMP systems today is the memory interface. Without an efficient memory system, high-performance processors in an SMP configuration are generally idle, simply giggling to themselves while they wait for data to be delivered from the memory. High performance can only be achieved in an SMP system with an efficient memory system.

One of my favorite systems is the Cray CS6400, which has up to 64 processors sharing a common memory across four memory buses rather than just one. This $4M supercomputer, which, by the way, is designed for business applications, uses Sun SuperSparc processors that are clocked at only 60 or 85 MHz. This computer achieves its ultra-high performance not with high-speed processors that are idle much of the time, but with an innovative memory interface that reduces the memory contention.

The ASCI Option Blue Pacific supercomputer that IBM and the U.S. Department of Energy are developing jointly achieves its high performance through the use of another innovative memory subsystem. In Chapter 2, I described that memory subsystem and showed how the AS/400 is using a version of that subsystem to achieve scalable SMP performance for 8- and 12-way processors. Using the fairly modest-performance, second-generation Apache processors, this memory subsystem has allowed the AS/400e series to achieve a performance level several times higher than earlier systems could achieve with the higher-performance, first-generation Muskie processors. The 12-way Apache systems are now challenging the performance of IBM’s biggest mainframe systems.

The production model of the Option Blue supercomputer is scheduled for demonstration in December 1998. At that time, it will be the world’s fastest and largest supercomputer. This supercomputer uses a new higher-performance implementation of the memory subsystem in the Apache systems. This new implementation allows higher-speed processors to be efficiently utilized in an even larger SMP configuration.

Our fourth generation of PowerPC processors uses the new implementation of the memory subsystem to achieve ultra-high performance systems. These processors can efficiently support up to 16-way configurations. This fourth generation of 64-bit PowerPC processors has various levels of performance, ranging from about 250 MHz at the low end to perhaps as high as 800 MHz. Needless to say, we expect the overall system performance to continue to rise dramatically over the next few years.

Of course, processor performance alone is not enough to achieve high system performance. We in Rochester believe in building balanced systems. Memory, disk, and I/O capacities and performance will increase as rapidly as processor performance. In Chapter 12, I present the benchmarks we use to measure system performance, now and in the future. I also show how the AS/400e series measures up against some other computer systems.

We also will make enhancements to save/restore, IPL, and recovery to balance the growth. Finally, to protect the hardware investments of our customers, the newly designed AS/400e series packages support all the enhancements just discussed. Getting a hardware performance improvement is as simple as replacing processor cards.

Years ago, a few of us who designed the AS/400 architecture speculated about when we would have supercomputer-class processors, hundreds of gigabytes of memory, and multiple terabytes of disk on a single system. Others scoffed at the idea of building a system architecture that could accommodate such unthinkable capacities. They said we would never build systems that big. It seems that “never” has arrived.

Clusters and Continuous Availability

In case the single-system performance and capacity improvements just described are not enough, you can always connect up to 32 AS/400s together in a cluster. An AS/400 cluster certainly provides a way to increase performance and capacity, but more and more, a cluster is being used to provide a continuous-availability solution for AS/400 customers who require 24 hours a day, 7 days a week (24 × 7) operations. Single systems cannot achieve that continuous availability.

Digital Equipment Corporation originally pioneered clustering as a means to provide scalability for its VAX systems. Over the years, clustering gained popularity in the Unix and MVS markets, primarily as a means to provide higher levels of availability. Recent announcements of new cluster support for systems such as Windows NT have put the spotlight back on this technology. With so many businesses moving to a networked world that never sleeps, the requirement for 24 × 7 continuous-availability computing is becoming a mainstream server requirement.