)
Figure 10.1 Hardware I/O Structure
| Previous | Table of Contents | Next |
The strategy of the AS/400 is to adopt new I/O structures that include key industry I/O bus and device-attachment standards. The PCI bus has rapidly become today’s industry standard. In addition to supporting the SPD bus, the AS/400 now directly supports the PCI bus. As we will see, the e-series implementation of the PCI bus balances the serviceability and reliability of the SPD bus structure with the commodity components available with PCI. Over time, other emerging standard interconnection buses, such as the ANSI Fiber Channel Standard, also may be incorporated into the AS/400.
One of the reasons for moving to PCI is cost. PCI adapter cards are generally less expensive, because they do not need a separate IOP for each adapter, as SPD adapters do. One way to reduce the expense of the SPD adapters is to use a Multifunction IOP (MFIOP) card. An MFIOP contains one IOP and allows a variety of “daughter” cards that have no IOPs to be plugged into the multifunction card. These daughter cards are often called I/O Adapters or IOAs. With this arrangement, multiple IOAs can share a single IOP, thereby reducing the overall cost.
Even with the MFIOP approach, the PCI adapter cards are less expensive than SPD cards, because of the packaging. Each SPD adapter card is contained in an aluminum “book” package. This book design has proved to be a very good way to package adapter cards, but it is more expensive than the PCI cards, which require no separate packaging. SPD books are then plugged into a special SPD card cage that is also more expensive than the PCI card boards found in a typical PC.
The transition to PCI is occurring in phases, starting with the low-end models of the AS/400e series. All of the smaller e-series models support only the PCI bus and only PCI adapters, which means these smaller models can compete very aggressively with PC servers (which use the lower-cost PCI adapters and boards). The middle of the e-series product line supports PCI adapters and optionally can support SPD adapters. The high-end models of the e-series initially support only the SPD bus and SPD adapters, with PCI support staged in a later release. Let’s look now at how PCI is supported in the various models.
The AS/400e entry server (otherwise known as Eiger), which was first introduced at V3R7 as the Advanced Entry, contains only a PCI bus. These e-servers use a new form of an IOP. Whereas a conventional IOP supports the interface to a specific type of device, this new IOP supports the PCI bus interface. This single new IOP can support up to 16 PCI adapters. This is similar to the SPD MFIOP approach with one IOP and multiple IOAs. The new IOP itself is integrated as a component on the Eiger planar board. This planar board looks very much like a motherboard in a conventional PC. PCI adapter cards then plug directly into this planar board.
The use of the new IOP to interface between the AS/400 and the PCI bus lets us provide the same level of serviceability and reliability that we do for the SPD bus. The IOP lets us isolate the PCI bus from the main processor, which gives us an advantage over PC servers that have to use the main processor for error handling or service operations. I should also note that the processor used for all of these new IOPs is a PowerPC. Before this time, IOPs used in individual SPD I/O adapters were microprocessors from various vendors, mostly Motorola. The strategy is to use PowerPC processors for all future IOPs.
The same IOP used in the Eiger is used in the midrange models that are packaged in the Millenium box. The base I/O devices (such as internal disks, CD-ROM, and tape) use PCI. These are the only adapters supported at the low end of the midrange models. Thus, these models support only PCI, similar to Eiger. The upper end of the midrange models optionally allows a separate SPD card cage or a separate PCI card board to be added inside the Millenium box. These boxes then can be configured to support only PCI adapters or a combination of PCI base adapters and SPD adapters.
The high-end models of the AS/400e series, packaged in the tall Mako boxes, initially support only the SPD bus and SPD adapters. Because most large systems are installed as upgrades for existing AS/400s, supporting only SPD adapters is a reasonable approach. Over time, the demand for PCI adapters in these large systems will increase, and we will add that support. To illustrate the I/O structure in these new Mako boxes, I use the 12-way SMP configuration from Chapter 2.
Figure 10.1 shows this I/O structure. This figure is essentially Figure 2.6, which shows the 12-way SMP configuration, but with the I/O added. For the Mako boxes, the System Area Network (SAN) provides the interconnection of all system I/O.2 Notice that the local 6xx address and data buses are serialized by the I/O bus interfaces and distributed via one or more SAN interconnections. The SAN interconnections enable the attachment of multiple I/O buses to the processor complex in a loop topology, as shown in the figure. The high-end models of the AS/400e series include an expansion box separate from the Mako box. This expansion box contains SPD bus adapters and is connected via a SAN interconnection. Each SAN interconnection can be either copper or optical fiber, depending upon the distance between boxes. Figure 10.1 shows the attachment of both SPD and PCI buses. At V4R1, only the SPD bus attachment is supported. The PCI bus attachment is a later addition and is shown only to illustrate how the two bus attachments are similar.
2A SAN is a new class of network designed for very high speed interconnections of systems and devices at distances of 10 to hundreds of meters. This distance falls somewhere between direct connections inside a cabinet and a LAN.
Figure 10.1 Hardware I/O Structure
The IBM SAN supports the Scalable Coherent Interface Link (SCIL) protocol, which is based on the IEEE 1596 SCI standard modified by IBM to achieve the required data integrity for commercial customers. The AS/400 SAN implementation provides two full duplex interconnection ports for each I/O bus interface as shown in Figure 10.1. Each of the two ports consists of two unidirectional one-byte-wide data paths (one operating in each direction to provide the full duplex capability). These two data paths can be connected together to form the loop topology shown in Figure 10.1 that is used to attach the I/O cards. Two loops are shown in the figure. With a clocking rate of 250 MHz, each of these loops provides a bandwidth of 250 MB/sec.
| Previous | Table of Contents | Next |
){kind=link}