SLIC provides separate routines, one to handle each type of interrupt. When the hardware detects an interrupt, control is passed to one of these First Level Exception Handlers (FLEHs). We discuss how the hardware passes control in the next section. The FLEHs handle many of the frequently expected exceptions. If one of these routines handles the exception, control is passed back to normal instruction processing. If the exception is instruction-caused and has not been handled, the FLEH passes control to the Second Level Exception Handler (SLEH).

The SLEH can handle some of the other expected but less frequent exceptions, such as a lock exception on a system object. It also is responsible for sorting out the exceptions that cannot be handled in the SLIC. If the unhandled exception occurred while the system was executing an instruction translated from the MI, the SLEH passes control to the MI exception generator. If the unhandled exception occurred while the system was executing a SLIC instruction, the SLEH passes control to the Third Level Exception Handler (TLEH).

The TLEH gets control from the SLEH, the machine check handler, if the machine check occurred during the execution of a SLIC routine, or during any other SLIC routine that has detected an exception. The TLEH first invokes the Component Specific Exception Handlers (CSEHs) that were set up by various SLIC components.

The CSEHs are defined by various SLIC components to free resources acquired while performing some operation, to clean up partial results of a failed operation, or to tolerate a failure in a particular code sequence. The CSEHs to be executed for a particular task are determined by CSEH blocks that are chained to the TDE of the task. Each CSEH block contains the address of the CSEH routine, the definer’s stack pointer, and any data needed by the CSEH routine. After all CSEHs for the task have been executed, control is passed back to the TLEH.

The TLEH then determines what to do with the exception. If the exception occurred in a SLIC task that was not running as part of an MI process, the task is destroyed. If the exception occurred in a SLIC task that was running as part of an MI process, control is passed to the MI exception generator.

The MI exception generator prepares the data for the process message, performs some clean-up operations, and sends the message to the queue space of the appropriate MI process.

Hardware Context Switching

Because the exception routines just described may need access to privileged instructions at the PowerPC level, the interrupt mechanism must be able to switch the state of the processor when control is passed to one of these routines. We usually describe this action as switching the context of the processor. The context is defined as the state of the processor with regard to privilege, relocation, storage protection, 64-bit mode, and so on.

In addition to just switching the context, the interrupt mechanism must perform context synchronization. Synchronization means the processor hardware must ensure that all instructions initiated before the interrupt will complete execution in the context in which they were initiated. Then the hardware must ensure that the instructions following the operation will be fetched and executed in the context established by the operation.

In Chapter 8, we looked at the Machine State Register (MSR) and the meaning of some of the bits in this register. The PowerPC architecture for the MSR defines several other bits, some of which we described in the preceding section. Because we have already covered the ones that are related to the topics we want to discuss, we will not discuss the remaining bits. What is important to understand is that the settings of all the bits in the MSR determine the context of the processor. The setting of these bits can be altered when a processor interrupt occurs.

The System Call (sc) instruction can be used to call a SLIC routine when it is necessary to change the context of the processor. This instruction can be used within translated MI programs to call upon the SLIC part of the operating system to perform some service. As we just saw, when the sc instruction is executed by the processor, a System Call interrupt is generated. Readers familiar with the System/370 may recognize the sc instruction in the PowerPC architecture as being very similar to the Supervisor Call (SVC) instruction in the System/370 architecture. The execution of either of these instructions causes an interrupt to occur. The PowerPC architecture has its roots in the original 801 minicomputer, which was defined in the middle 1970s. The 801 architecture was heavily influenced by the mainframe architecture of the time, the System/370. In some sense, the MSR is analogous to the Program Status Word (PSW) of the System/370.

When any interrupt occurs, the PowerPC processor hardware first performs context synchronization to ensure the interrupt processing operation is not initiated until all instructions already in execution have completed to a point where they have reported all exceptions they will cause. Note that each interrupt has a priority, so if more than one interrupt is pending, the highest priority one is first selected. The effective address of the instruction that was executing when the interrupt occurred is then saved in a special 64-bit processor register, called the Machine Status Save/Restore Register 0 (SRR 0). In the case of a System Call interrupt, the effective address of the instruction following the sc instruction is stored in SRR 0. Next, selected bits from the current MSR are saved in another special 64-bit processor register, called the Machine Status Save/Restore Register 1 (SRR 1). Finally, still other bits in SRR 1 are loaded with information specific to the type of interrupt that occurred.

After saving the current machine status, the interrupt hardware causes some of the bits in the MSR to be altered. The new MSR bit settings are specifically defined by the architecture for each interrupt type. In particular, the relocation bits (MSRIR and MSRDR) are always turned off so the interrupt routines will use real addresses and never get a page fault. After modifying the MSR bits, the interrupt hardware then causes the next instruction to be fetched from an address that is a fixed offset from a base address. The Power-PC architecture also defines the specific offset to be used for each type of interrupt. Another bit in the MSR, called the interrupt prefix, selects one of two base addresses to be used.

The result of the hardware interrupt processing just described is to transfer control to the first instruction of one of the SLIC interrupt handlers described in the previous section. The context of the processor also has been switched before this routine gets control so, for example, privileged instructions can be executed in this routine.