ILE Process Structure

Let’s get some of the acronyms out of the way first by defining the components that make up an ILE process:

•  Process Control Block (PCB) — The PCB is contained in the system object that represents an MI process. Earlier, we saw that this system object is called the process control space and, among other things, it contains the TDE for the process. The PCB also contains addresses of other components associated with the process, as we will shortly see.

•  Process Activation Work Area (PAWA) — The PAWA is a heap used for allocation of runtime structures, such as the activation groups. There is one PAWA per process.

•  Parent Activation Group (PAGP) — The PAGP is the root structure for the process substructure. It contains a list of all activation groups for the process. Contrary to what its name implies, a PAGP is not itself an activation group.

•  Activation Group (ACTGRP) — We have already introduced activation groups. The ACTGRP provides the storage resources (stack, static, and heap) for program activations. The ACTGRP is like a mini-process.

•  Tombstone Segments — These segments are used to construct process object pointers (POPs). POPs are “handles” to SLIC structures. A handle is used by many operating systems, including OS/2 and Apple Macintosh, as a way to indirectly point to a block of memory in a heap. Instead of giving direct addressability to the block, a handle points to a master pointer. The master pointer is typically in a fixed location and contains the address of the block. As these blocks are relocated in memory, only the address in the master pointer has to be changed. These segments are called tombstone segments because they do not give direct access to SLIC structures; that is, no way exists to get at the SLIC structures, even if the system security level allows access to these segments. The master pointer is in a memory area that can be accessed only by SLIC.

•  Process Queue Space — Every process has one or more send/receive queues (SRQs) to hold messages, and these queues are contained in the process queue space.

Figure 9.4 shows how these components fit together to form the ILE process structure. Notice that the PAWA contains the list of all the activation groups (the PAGP), along with all the activation groups. The figure shows four activation groups, although as we saw earlier, the minimum number is two. The first ACTGRP is always the default activation group for the system and the second ACTGRP is always the default activation group for the user. We are now at a point where we can look inside an activation group.

Figure 9.4  ILE Process Structure

ILE Activation Group

An activation group contains, or links to, several other components with strange names and acronyms. Let’s start with a definition of these components:

•  Program Activation Control Block (PACB) — A PACB is an addressing structure that is used during the execution of a program. It locates procedures and data that are bound to the program. There is one PACB per active program, and each PACB contains one or more Module Binding Vectors (MBVs).

•  Module Binding Vector (MBV) — The MBV is an addressing structure for a single module. It contains the runtime addresses of the data and procedures referenced by the module.

•  Activation Group Directory (ActGrp Directory) — The ActGrp directory is a symbolic directory used for late binding between data and programs.

•  Procedure Reference Table (PRT) — The PRT segments contain the procedure entry points used by interactivation group and procedure pointer calls. There is one PRT per activation group.

•  Heap List and Heap Spaces — The heap list identifies the heap spaces associated with the activation group. A heap space consists of a control segment plus multiple data segments. Heaps for MI and SLIC use are managed by a heap manager in SLIC.

•  Auto Storage Segments — These segments contain the stack used for automatic storage by the activation group.

•  Static Storage Segments — The static storage for the activation group is contained in these segments.

Figure 9.5 shows how these components fit together to create an activation group. To summarize, we can say each process in the AS/400 has a PAWA. Within this PAWA is the PAGP and two or more ACTGRPs. Each ACTGRP has a PACB that contains multiple MBVs, an ActGrp directory, a PRT, a heap list, one or more heap spaces, auto storage segments, and static storage segments. Now, isn’t this perfectly clear?

Figure 9.5  ILE Activation Group

Exceptions, Events, and Interrupts

When something doesn’t conform to the general rule, we usually say it is an exception to the rule. Computer systems also take exception to the general rules of processing. In this section, we look at how exceptions, events, and interrupts are handled in an AS/400.

At the hardware level, it is usual to talk about interrupts. As described earlier in this chapter, an interrupt is an occurrence, other than a branch, that changes the normal flow of instruction execution. The interrupt may be caused by the execution of an instruction or it may be caused by some action outside of the running program, such as the completion of an I/O operation. The Power-PC architecture defines a full interrupt mechanism to allow the processor to change state as a result of external signals, errors, or unusual conditions arising in the execution of instructions. We will see how this works later in this section.

Programs and processes at the MI know nothing about interrupts at the hardware level. However, an interrupt that occurs as a result of MI program execution must be reported at the MI. The SLIC is responsible for detecting, handling, and reporting these interrupts at the MI.

Exceptions and Events at the MI

MI distinguishes between an exception and an event. An exception is defined as either a machine-defined error detected during the execution of an instruction or a user-defined condition detected by a user program. An event, on the other hand, is defined as an activity that occurs during machine operation that may be of interest to machine users. Exceptions are synchronous, meaning they are caused by the execution of an instruction, while events are asynchronous, meaning they are caused by actions outside the currently executing instruction. In general, however, the two are very similar.