Memory Access Modes
All memory accesses on the AS/400 are performed under the control of four mode-control bits: Write Through (W), Caching Inhibited (I), Memory Coherence (M), and Guarded Storage (G). One of the characteristics of a RISC processor is the capability of the software to control the hardware. These four bits are set by the SLIC to provide some of that control on a page basis. For all translated accesses, these bits come from the PTE. For all real addresses (E = R or relocate turned off), these bits are assumed to have values 0, 0, 1, and 1. The W and I bits control how a processor uses its data cache. The M bit specifies whether the processor must ensure memory consistency. This usually applies to multiprocessor systems. The G bit controls whether out-of-order fetching of data and instructions is permitted. Following is more detail about each of these bits:
|
| W
| Write Through
|
|
|
| If W = 1, any update to the data cache also must be written to the main memory. If the data in a main memory page must always be current because, for example, it is shared by multiple processors, this bit will be set on. A load instruction will use the copy in the cache if it is there. A store will update the copy in the cache and in the main memory.
|
|
| I
| Caching Inhibited
|
|
|
| If I = 1, the memory access is made to the location in main memory. During the access, neither the accessed location nor the block in memory containing the location are copied to the cache. This is useful for large blocks of data that are only read sequentially and would flush the contents of the cache if not inhibited.
|
|
| M
| Memory Coherence
|
|
|
| If M = 1, the processor must enforce data coherence. Coherence refers to the ordering of writes to a single memory location. For improved performance, the memory control hardware sometimes can write data to memory in a different order than the processor issued the store instructions. But this can be a problem if multiple processors are sharing a location in memory and the ordering of stores to that location is important. By setting this bit on for the page, the stores by all processors to the same location are serialized.
|
|
| G
| Guarded Storage
|
|
|
| If G = 1, out-of-order fetching of data and instructions from the page is not allowed. To achieve higher performance, some processors can execute an instruction before it is known that the sequential execution model requires it. Suppose, for example, that a particular processor has an instruction pipeline that is not being used during a given cycle. If there is an instruction farther ahead in the instruction stream that could execute in this pipeline, the processor can start the execution. This is called out-of-order execution. Of course, the machine must appear to follow the sequential execution model. If a branch or an exception occurs before the processor would normally get to the out-of-order instruction, the state of the processor must be rolled back to appear as if it never executed the instruction. Sometimes a memory area may not be well-behaved with regard to speculative operations. For example, an I/O device may be using a memory area and a speculative load to this device may cause the device to perform unexpected or incorrect operations. If the SLIC wants to ensure that this does not occur, the G bit for the page can be turned on.
|
Page Protection
Our final topic within address translation is memory protection. The memory-protection mechanism in an AS/400 provides protection on a page-size block. This is different from the tag bits, which protect pointers on 16-byte memory blocks. Another big difference is that tags do not prevent access to a pointer — they detect modification after the fact. The page-protection mechanism can prevent the page from being read or written.
The PTE contains two page-protection (PP) bits. These two bits together with the MSRUS bit are used to determine the type of access allowed to the page. Recall that the MSRUS bit is set to 1 when user code is executing and to 0 when operating system code is executing. Figure 8.7 shows the type of page access allowed for each bit setting. Read/write access means the executing program can read and write to the page; read-only access means that the program can read but not write to the page; and no access means the program can neither read nor write to the page. Figure 8.7 also shows the primary uses for these protection settings. For example, notice that all MI-generated code and constants are contained in pages that are read-only. You can use Figure 8.7 to determine the types of accesses allowed to a page based on the value of the key and the settings of the PP bits.
Figure 8.7 Page Protection Processing
Wow! it’s great to get out of those spicy sections! Let’s look at disk management and how it fits into single-level store. This topic should be a lot milder for most of our tastes. Is it hot in here?
Disk Management
The component in the SLIC responsible for managing AS/400 disks is called auxiliary storage management. This disk-management component has several responsibilities. These include
- • Managing auxiliary storage pools (ASPs). An ASP is a set of one or more disk units.
- • Creating, extending, truncating, and destroying segments on disk.
- • Managing the free space on each disk unit.
- • Maintaining the directories that relate virtual addresses to disk locations.
Auxiliary Storage Pools (ASPs)
The original idea for the System/38 was to keep any knowledge of disk drives totally below the MI. No application or operating system code above the MI was ever to know there were disks attached to the system. Technology independence means no software should ever be dependent on the specifics of an I/O device. However, the software certainly needs to know about devices such as terminals and printers. So why doesn’t it know about disks?
The answer relates to the fact that some of us in the System/38 community held a strong belief that disks did not have much of a future. After all, how long can a technology that depends on a coating of rust on a platter last? We believed disk technology would be replaced by one of the upcoming semiconductor technologies. Two new semiconductor devices in the mid-1970s showed some promise of replacing disks: Perhaps magnetic bubbles or charge-coupled devices would be the ultimate answer. Or maybe main memory technologies would become so inexpensive that no other form of storage would be needed.
)
){kind=link}