If the high-order 3 hex digits of an effective address are 800, the address is an E = R address. Parts of SLIC must work with real addresses and be able to address anything in memory. Much of the memory-management code also must operate with these addresses. A part of the effective address space is set aside for these E = R addresses. Not coincidentally, there are 2⁵² of these addresses (64 bits minus the 12 high-order bits for 800) to match the real address range.

When the hardware detects an E = R address, it checks the problem state bit to see whether the process that generated this address can execute privileged PowerPC instructions (MSR_PR = 0). If so, the remaining 52 bits in the E = R address are passed directly to the main memory as a real address. If MSR_PR = 1, a given processor implementation will either generate an exception or treat the address as a translated address — different PowerPC processors react differently. With a valid E = R address, there is no translation overhead. We like to say that using an 800 number is a toll-free way to access the memory.

The PowerPC architecture uses a range of addresses, called the direct-store addresses, to access the I/O space, which we briefly introduced in Chapter 2. An external address space is defined, which to the processor looks like a part of the memory. Of course, this address space is not part of the memory; rather, the address is used to identify a particular I/O device attached to the system. Typically, devices in any system are attached to an I/O bus. In Chapter 10, we will see that AS/400 devices are attached to I/O processors, which in turn are attached to I/O buses. This direct-store address is used in the AS/400 to identify both an I/O bus and an I/O processor attached to the bus.

With this type of architecture, which is often called memory-mapped I/O, a special set of instructions exclusively used by the processor to communicate with the I/O devices is not needed. Instead, any load or store instruction can be used to pass commands and data to the devices using this external address space. A direct-store address is a mapping of an effective address to this external address space.

If the high-order 3 hex digits of an effective address are 801, the address is an E = DS address. When the hardware detects an E = DS address, it checks the problem state bit to see whether the process that generated this address can execute privileged PowerPC instructions (MSR_PR = 0). If so, the remaining 52 bits in the E = DS address are passed directly to the I/O space. Like the E = R addresses, E = DS addresses have 2²⁸ effective segments. If MSR_PR = 1, a given processor implementation will either generate an exception or treat the address as a translated address.

If the high-order 3 hex digits of an effective address are neither 800 nor 801, the address is a translated address. Because the system is in the tags-active mode, the effective address is the virtual address. This virtual address is translated into a real address using the page table.

Figure 8.4 shows the steps involved in the address translation for tags-active mode. The high-order 40 bits of the effective address are called the effective segment identifier (ESID) and the low-order 24 address bits are called the offset. As shown in the figure, the offset is further divided into a page offset and a byte offset. Each of these offset fields is 12 bits long. The page offset identifies the page in a segment, while the byte offset identifies the byte in the page.

Figure 8.4  Steps Involved in Address Translation (Tags Active)

The first step in the translation process is to create the virtual segment identifier (VSID), which in the tags-active mode is simply the ESID. The virtual address, like the effective address, is 64 bits long and has a 24-bit offset. The VSID and the page offset portions of the virtual address make up the virtual page number (VPN). From Figure 8.4 we can see that the VPN is 52 bits long. The VPN is used to look up the real page number (RPN) in the page table. The RPN is the number of a page frame in memory, not the number of a page on disk. The byte offset is always passed from the effective address to the virtual address to the real address. The byte offset identifies the byte in a 4K page and never participates in any of the translation process.

For comparison purposes, Figure 8.5 shows the steps involved in the address translation for tags-inactive mode. This translation mechanism is not used for the AS/400, but the figure shows both the similarities and differences between the AS/400 address translation and the translation used for an operating system such as AIX. In this case, the ESID is used to access the segment table, and the VSID is found in that table. The page table access, which we discuss shortly, is the same for both tags-active and tags-inactive modes. One further point to note is the size of the fields in the addresses. For the tags-inactive mode, the offset portion (page plus byte fields) of the effective and virtual addresses is 28 bits, as opposed to the 24 bits of the tags-active mode. The 28 bits was selected to match the number of offset bits in the original 32-bit POWER architecture that is still used in some RS/6000 processors.

Figure 8.5  Steps Involved in Address Translation (Tags Inactive)

We are going to skip an in-depth look at the segment table and focus our attention on the page table. Suffice it to say the implementation of the segment table is very similar to the page table. The general approach used to look up an entry in the segment table is the same as the one used to look up an entry in the page table. In an AS/400, the virtual-to-real address translation that uses the page table is more important than the segment translation, because most effective addresses bypass the segment table.

Virtual-to-Real Address Translation

The data structure in memory that contains the RPN is the page table. The approach to building a page table in most non-AS/400 virtual memory implementations is to have one entry in the table for every page in virtual memory. The VPN is used as an index into the page table to select one of the entries. The selected entry contains the RPN, which then becomes part of the real address.