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We already have introduced some characteristics of the AS/400’s memory model in this chapter. Let’s review a list of these characteristics, together with some we have not seen before (we will discuss all these characteristics in more detail in the next couple of sections):
Again, the characteristics listed are for the tags-active, 64-bit processor implementations the AS/400 uses.
The address translation process is controlled by the tags-active or tags-inactive mode and by the state of the processor. A special register in the processor, called the Machine State Register (MSR), defines the state of the processor. The bits in this register tell the processor how to perform certain operations, such as address translation. In Chapter 9, we look at this register and see how the bits in the register can be altered. A few words about some of these bits in the MSR and their settings are needed to help you understand address translation. The bits are
The address translation process uses the 64-bit mode bit (MSRSF) to determine the size of the addresses. For example, in the 32-bit mode, the effective address is defined in the PowerPC architecture to be only 32 bits long. With the tags-active mode in the AS/400 processors, only the 64-bit mode setting is recognized by the hardware. Thus, SLIC, which controls the settings of the MSR bits, will set only the 64-bit mode.
The instruction relocate bit (MSRIR) and the data relocate bit (MSRDR) allow the processor to operate in the real addressing mode. When SLIC turns off relocate, the address translation mechanism is bypassed, and the low-order 52 bits of the effective address are passed directly to the memory subsystem as a real address. The memory subsystem is defined as the cache memories and the main memory. The PowerPC architecture supports a cache model in which there are separate caches for instructions and data. For this reason, separate relocate bits are provided for instructions and data. This model is called a Harvard-style cache.6
6In the early 1940s, Harvard University, with funding from IBM, developed a series of computers, called Mark. The Mark-III and Mark-IV had separate memories for instructions and data. The term Harvard architecture is used to describe machines with separate memories.
The C2 security bit (MSRC2) originally was defined to force the address-translation mechanism to use the segment registers for all user accesses when the processor was operating in the tags-active mode and C2 security was enabled. Going through the segment tables ensured that the operating system could monitor and log all the objects each user accessed when C2 security was enabled. Although this bit still exists in some PowerPC processors, it is not used for the C2 auditing function. Instead, when level 50 security (C2 security) is specified, the security component of the SLIC monitors and logs user access to objects directly without using the segment registers.
The problem state bit (MSRPR) is used in the address-translation process and for memory protection. The problem state bit defines whether the processor can execute the privileged instructions in the PowerPC instruction set. These privileged instructions should not be confused with MI privileged instructions (such as the PWRDWNSYS instruction we saw in Chapter 7) — only SLIC executes privileged PowerPC instructions. An example of a Power-PC privileged instruction is one of the tag instructions such as the lq we discussed in an earlier section.
The user state bit (MSRUS) supports the AS/400’s security level 40 and up. This bit distinguishes system state versus user state for an AS/400 process. The user state bit determines whether the authority can be put into a pointer, and whether MI privileged instructions can be executed by the process. The user state bit is also used for memory protection. Note that the user state bit is also used only in the tags-active mode.
Figure 8.3 shows the PowerPC address translation with tags active. The hardware checks the 64-bit effective address generated by a program to determine whether it is a translated address, an E = R address, or an E = DS address. The high-order 12 bits (3 hex digits) of the effective address are used to make this determination.
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Figure 8.3 Address Translation with Tags Active
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