Hardware Protection for Pointers
We realized we needed some form of hardware memory protection for pointers. Many of the larger systems at the time, such as the System/370, used special bits in the hardware to provide memory protection. The hardware used these bits to allow or inhibit user access to some block of bytes in the memory. These protection bits usually were kept in a separate hardware memory array, where the user could not get at them. With every access to memory, this special hardware array was checked to determine whether the user was allowed to access the block in memory. This type of memory protection was usually on a page-sized physical block of memory.
We originally hadn’t planned to implement this type of memory protection in the System/38 hardware, because we didn’t think we needed it. Our protection was at the object level. But when we realized we needed some form of hardware protection, we briefly considered protection on a page-sized block. But that approach was expensive and not exactly what we wanted. Ideally, we would have protection for every 16 bytes in memory, because a pointer occupies 16 bytes. But for performance reasons, we wanted to put pointers anywhere, and the expense of putting in a separate hardware array with protection bits for every 16 bytes in memory was prohibitive. Then we found the answer. We had extra bits in our memory for our error-correcting code (ECC). We would use an ECC bit for memory protection.
Computer memories occasionally make errors because of voltage spikes on power lines or other causes. To guard against errors, most memories use error-detecting or error-correcting codes. When these codes are used, extra bits are added to each memory word. A memory word contains the number of bits that can be read from or written to memory in a single operation. When data is read out of memory, the extra bits are checked to see whether an error occurred in memory.
The simplest form of error detection is to add a single parity bit to the memory word. The value of the parity bit is chosen so the number of 1 bits in the memory word, including the parity bit, is always an even number. If an error occurs in memory that causes any bit to change from 1 to 0 or from 0 to 1, that error will be detected when the memory word is read out and the number of 1 bits is no longer even. Parity provides single-bit error detection, but it doesn’t tell which bit failed. Parity, usually used for PC memories, can detect whether an odd number of bit errors occurred, but it tells nothing if an even number of bit errors occurred in the memory word.
Most computers that are used for commercial processing, such as the AS/400, use additional bits in their codes to provide both error detection and correction. These additional bits can detect all single- and multiple-bit errors, and they can even identify which bit failed on a single-bit error. Thus, the hardware can correct errors and continue processing. The value of error correction is obvious to anyone who has powered on a PC and received the message “memory parity error.” Nothing happens with that PC until the bad memory module is replaced. For this reason, many high-end PCs now are using ECC memories.
The original System/38 hardware had a 32-bit (4-byte) memory word. The ECC for this word size required an additional 7 bits. For every memory word, we needed 39 bits — 32 for data and 7 for ECC. Our memory technology in those days was always packaged in 8-bit increments, meaning our memory word was actually 40 bits wide. We had an extra bit for every 4-byte word in memory, and that bit was to become our memory-protection bit. We called it a tag bit.
A pointer occupies 16 bytes in memory. We decided to always store pointers on 16-byte memory boundaries (the low-order 4 bits of the memory address are all zeros). From a terminology standpoint, we usually call this a quadword, which means it is a 16-byte field aligned on a 16-byte boundary. Likewise, we have doublewords and words, each aligned on 8- and 4-byte boundaries, respectively. Within the computer industry, the name word is generally accepted to mean 4 bytes.
A pointer in the original System/38 occupied four consecutive 4-byte words in memory, each with its own tag bit. We decided to have the tag bit for every memory word set to 1 if that word contained any of the four parts of a pointer. If there was no part of a pointer in the word, the tag bit was set to 0. The pointer itself needed only one tag, so we said if all 4 bits in the consecutive four memory words were set to 1, then the pointer had a logical tag of 1. If any of the 4 bits was 0, then the pointer had a logical tag of 0.
Later implementations of the AS/400 have a 64-bit (8-byte) memory word. A 64-bit memory word requires 8 ECC bits; so with the tag bit, the AS/400 memories are packaged 73 bits wide. We still keep pointers on 16-byte boundaries, and each pointer has one logical tag bit. For the AS/400 with the 64-bit memory word, the two tag bits in the consecutive two words that hold the pointer must both be 1 for the pointer to have a logical tag of 1. If either tag bit is 0, then the pointer has a logical tag of 0. To keep with the industry terminology, we call the 64-bit memory word a doubleword.
Whenever a write to memory occurs in an AS/400, the memory-control hardware creates the ECC and stores it with the memory word. As part of this write operation, the memory-control hardware also turns off the tag bit in the memory word (sets it to 0). Any standard instruction that writes to memory will always result in the tag bits for the words written being set to 0.
Tags-Active Mode
In Chapter 2, we talked about extensions to the PowerPC architecture. One of the extensions we discussed was a tags-active mode. When a PowerPC processor is configured in this mode, additional instructions are available that do not appear in the tags-inactive mode. We said there were 25 instructions added for the AS/400 and they are available only in the tags-active mode. These include instructions to allow loading and storing multiple quadwords to and from the registers. There are also instructions for decimal arithmetic, system call/return functions, and select instructions to test bit settings in control registers. Six of the new instructions support tags.