The Future of Memory Switches

If hierarchies of caches are good, why not have hierarchies of switches? In fact, this is exactly what we will see in the future. In our previous example, each processor was connected via a 6xx bus to each of the four switches. We could instead have one switch per each 4-processor node, which we would probably call a node controller. These node controllers then could be connected to a set of switches, which are then connected to a bank of memory cards. In fact, we could have the node controllers connected to multiple sets of switches, and these multiple sets could each have their own memory banks. In this way, we could achieve a very large SMP configuration. Look for such configurations with Rochester’s fourth generation of processors.

Remember the IBM ASCI Blue Pacific computer? This computer will have 512 processor nodes, each with eight processors and a switched UMA memory subsystem. Don’t look for such a big AS/400 version any time soon, but isn’t it nice to know that such configurations are possible even if they are not too practical? After all, the code name for the System/38 was Pacific, and we did want to build some really big systems. Let’s see, if we plugged in Rochester’s next generation of PowerPC processors, hmm….

Conclusions

A 64-bit processor is the standard in the computer industry. All AS/400 RISC processors are 64-bit “industrial-strength” processors capable of delivering the function and performance demanded by commercial systems and servers. They are members of the PowerPC family of RISC processors that will carry the AS/400 into the next century.