The First- and Second-Generation Cobra Processors
Like the Muskie processors, the Cobra processors implement the 64-bit extended PowerPC architecture. Similarly, they are superscalar designs to take advantage of instruction-level parallelism. Functionally, the two processor families execute the same application-level instruction set. There are slight differences between the two in the optional instructions that are implemented. For example, Cobra was intended for the middle and lower models of the AS/400, so instructions to support characteristics such as multiprocessing were not included.
The Cobra processors were developed in Endicott. Four versions of Cobra have been built. The two Cobra processors announced in the 1995 RISC AS/400 systems are the Cobra-4 and Cobra-CR. The CR stands for cost reduced. The Cobra-CR is a Cobra-4 processor that can run at only 50 MHz, which is the slowest speed of the Cobra-4. The Cobra-4 can also run at higher speeds. We will look at its characteristics shortly.
For the purpose of testing the new operating system software, the Endicott design team designed a special version called Cobra-0. Cobra-0 was used only for testing and was not shipped in any AS/400. A small team in Rochester designed a fourth version for use in the original Advanced 36 system announced in 1994. It was called Cobra-Lite because 17 of the required PowerPC instructions were left out.8
8Cobra-Lite is the first generation of RISC processors to appear in an AS/400. Later Cobra designs, which implement the full PowerPC instruction set, are considered to be a second generation of the Cobra-Lite design.
The design objective for Cobra was to integrate the processor and the memory interface on a single chip. This single chip contains 4.7 million transistors. The I/O bus interface is on a separate chip, which allows this processor to be used with different I/O interfaces. To accomplish this, the Cobra uses a CMOS technology instead of BiCMOS. Specifically, it is implemented in a technology IBM calls CMOS-5L. The result is an implementation that dissipates less heat than Muskie and can be used in a smaller package with less cooling required. For this reason, the Cobra processors were the only ones packaged in the original physical boxes that were announced for the Advanced Series in 1994.
Like Muskie, Cobra has five pipelines, but it can dispatch only three instructions in a given cycle (it is a 3-way superscalar design). The three instructions are
- 1. A branch instruction (including a condition register instruction)
- 2. A load/store instruction
- 3. A fixed-point arithmetic instruction (including a logical, shift, or rotate instruction), a floating-point instruction, or a condition-register instruction
The three pipelines (fixed-point, floating-point, and condition-register instruction execution) share the third dispatch slot.
The initial Cobra processors had clock rates of 50 MHz and 77 MHz, but the design is capable of higher speeds, as we will soon see. To sustain this rate, Cobra has a 4K (on-chip) instruction cache and an 8K (on-chip) data cache. These are small caches compared to the Muskie design. Putting large caches on a single-chip processor is difficult because of the space limitations, so processors such as Cobra use a hierarchy of caches. The small on-chip caches (called the level 1 or the L1 caches) are backed up with a larger off-chip cache (the level 2 or L2 cache). Cobra can have a 1 MB (off-chip — on separate chips) L2 cache.
The Third-Generation Apache Processors
The AS/400 for 1997 features a new processor design. This single-chip PowerPC processor was developed in Rochester as the Apache processor. The middle and high-end models of the AS/400e series use this processor. Cobra continues to be the processor for the low end of the product line.
You can think of Apache as a third-generation design because the engineers started with the Cobra design and added many improvements and new features. One new feature is a multiprocessor capability that was not available on Cobra. This is the first single-chip AS/400 processor to support up to 12-way SMP configurations; even Muskie supported only 4-way SMP configurations.
Unlike either Cobra or Muskie, Apache implements the full PowerPC architecture. Apache has a tags-active mode to support the single-level store of the AS/400, and it has a tags-inactive mode to support the standard PowerPC addressing model. It also uses the standard PowerPC 6xx data and address buses for off-chip connections. This means that an Apache chip can connect to any support chips that are designed to work with the PowerPC 6xx family of processors. In Chapter 10, we will see how this feature is helping to transform the I/O structure of the AS/400e series. As a result of this full PowerPC implementation, Apache is the first Rochester-developed processor ever to be used outside of a Rochester system. Models of both the RS/6000 and the AS/400e now use Apache processors.
Like the Cobra design, Apache is a single-chip, 64-bit, superscalar RISC processor. Figure 2.5 shows a block diagram for this processor, which is implemented in IBM’s newest CMOS-5S technology. This more dense silicon technology produces a cycle time of 8.0 nanoseconds (125 MHz), although slower-speed versions of the chip are used in some AS/400e series models. Using CMOS greatly reduces the amount of heat that must be dissipated from the processors. As a result, up to four Apache processors are packaged on a single card.
Figure 2.5 Apache Processor Block Diagram
The memory subsystem design is the biggest change for this new processor design. We will see in a following section that systems with Apache processors use a totally new memory subsystem designed to move massive amounts of data without slowing down the processors. Even though the processor cycle times are not as fast as the Muskie processors, this new memory subsystem makes the Apache more scalable for SMP configurations, enabling even higher performance models of the AS/400e series than were previously available.
Before continuing, we need to look at the new physical packages that were announced with the Apache processors. Three of the original black boxes in the AS/400 Advanced Series (known as Apex, Cedar Key, and Key Largo) have been replaced by two new black boxes (Millennium and Mako). The package introduced for the Advanced Entry (Eiger) remains unchanged in the AS/400e entry server. We changed packages for several reasons.
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