The six chips that make up a single processor include a Processing Unit (PU) chip, a Floating-Point Unit (FPU) chip, and four copies of a Main Store Control Unit (MSCU) chip. The PU chip contains the instruction cache, the branch unit, and the fixed-point unit. The instruction cache has 8K, organized 32 bytes wide. The cache can fetch 32 bytes (eight instructions⁷) per cycle from memory. The 32-byte data paths are designed to transfer large amounts of data in a single cycle. Even the register stack in the fixed-point unit is designed to load or store four 64-bit registers in a single cycle.

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⁷All PowerPC instructions are 32 bits wide for both the 32- and 64-bit processors.

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The FPU is contained on a single chip and supports the IEEE standard for floating-point. The design of the FPU is such that it can produce a result every cycle, giving this processor its very high floating-point performance. Four instructions per cycle are passed from the PU chip to the FPU chip on the 16-byte P-bus. All store data from the PU is also passed across the P-bus on its way to the data cache. Data for the FPU is fetched from the data cache at a rate of 32 bytes per cycle. All store data from either the FPU or the PU is passed to the data cache across the 16-byte store bus.

The MSCU provides the data cache as well as the interface to the memory. All four chips work together to provide the 256K data cache and the interfaces to the data buses shown in Figure 2.4. The data cache accesses are pipelined so that 32 bytes of data are fetched and 16 bytes of data are stored each cycle. The MSCU supports multiprocessing by providing cache coherency across multiple processors.

In total, there are five pipelines in the PU and FPU, but only four instructions can be dispatched each cycle. The four instructions are

1.  A branch instruction (including an operation on the contents of the condition register)

2.  A load/store instruction

3.  A fixed-point arithmetic instruction

4.  A fixed-point logical, shift, or rotate instruction; or a floating-point instruction

The floating-point instructions are executed in the FPU, but they cannot be dispatched at the same time as a fixed-point logical, shift, or rotate instruction, which executes in the PU. Note that the load/store pipeline does both fixed and floating-point loads and stores. The multiple pipeline implementation allows parts of several instructions to be executing simultaneously.

Muskie also supports tightly coupled, shared memory, so it can support symmetric multiprocessing (SMP) configurations. Up to four-way multiprocessing was supported for this first-generation processor.

Besides being a fast RISC processor, Muskie was optimized for the needs of a commercial processor. A few of these characteristics will illustrate the point:

•  Commercial systems and servers must handle lots of data. The 16-byte- (128-bit) and 32-byte- (256-bit) wide buses let this processor handle massive amounts of data and instructions. Compare this to the typical 8-byte (64-bit) buses used in most high-performance RISC processors. These are designed for use in a workstation whose data requirements are far less demanding.

•  Even if a system can move large amounts of data, the cache memory is usually a bottleneck in most RISC designs. Muskie has a 256K, single-cycle data cache to overcome this bottleneck.

•  Because a branch instruction can stall a pipelined processor, RISC processors today implement some form of branch prediction just as the supercomputers do. Branch prediction used in most RISC processors is typically 80 to 90 percent accurate on a technical workload. The reason for these high percentages is that technical computing usually involves a lot of loop processing, where the processor re-executes an instruction loop several times. Branch prediction works well for this kind of processing. For a commercial workload, where there are far fewer loops, branch prediction may be as low as 50 percent accurate (a random guess would be as accurate). For this reason, rather than trying to guess which branch target will be needed, Muskie pre-fetches the instructions at both branch targets and begins to execute them (called speculative execution). This requires a very high bandwidth cache, which Muskie has, but it does achieve essentially 100 percent accuracy for all workloads.

•  Another important aspect of commercial processing is the need for high data integrity and high availability. Muskie implements full error-correction codes or parity on all off-chip signals. Various parity schemes are also integrated into most of the control and data-flow logic on each chip. Again, compare this with the typical workstation RISC processor, which rarely has anywhere near this level of error detection and correction.