Amazon Instructions

The PowerPC architecture defines privileged operations and instructions that only the operating system uses. These privileged operations and instructions are not used by the application programs. The tags-active mode enables the extensions that were added for the AS/400 and determines how the privileged operations and instructions are defined. For example, the address-translation mechanism needs to support both a single-level store with a single address space and a conventional store with a separate address space for each process. We use the tags-active mode to tell the processor to use a single-level store. The tags-inactive mode tells the processor to use the conventional PowerPC address translation.

Other extensions for the AS/400 include decimal-support instructions, some new load-and-store instructions, and some enhancements to an internal processor status register to improve branching. Rather than spending time now exploring how these instructions are used in the AS/400, let’s hold off that discussion for later chapters. Then we will be able to see exactly how each extended instruction is used.

To summarize the changes to the AS/400 architecture, and to put these changes into perspective with the PowerPC architecture, we need to review some numbers:

•  The 32-bit PowerPC architecture defines 187 instructions, with 11 of them being optional.

•  The 64-bit PowerPC architecture defines 228 instructions (187 from the 32-bit set plus 41 additional), with 21 of them being optional.

•  The Amazon architecture defines 253 instructions (228 from the 64-bit PowerPC set plus 25 additional), with 20 of them being optional. Note that the 25 additional instructions are available only in the tags-active mode. The tags-inactive mode supports only the 64-bit PowerPC instruction set. Also note that the definition of any architecture is dynamic and the exact numbers are subject to change.

AS/400 Processor Implementations

The first RISC processors used in the AS/400 supported only the tags-active mode. They also supported only the AS/400 I/O structure. This means they can run applications, but not operating systems, written for a standard PowerPC processor. Any other operating system running on one of these processors must use the facilities provided by the AS/400 operating system for such functions as I/O. In later chapters, we will see how this works.

The latest generation of RISC processors in the AS/400e series implements both the tags-active and the tags-inactive modes; in addition, they simultaneously support other I/O structures. These processors are capable of running any PowerPC operating system, and they are used in both the AS/400e series and the RS/6000. Follow-on processors likewise will implement both tags-active and tags-inactive modes for use in both the AS/400e series and the RS/6000.

The First-Generation Muskie Processors

Let’s examine the first-generation processor known as Muskie.⁶ Designed in Rochester, the Muskie processor was announced as the high-end processor for the AS/400 in 1995. At the time of its announcement, this was the fastest processor based on PowerPC technology, and the fastest microprocessor in IBM. This high-performance processor had originally achieved a cycle time of 6.5 nanoseconds, which equates to a clock rate of 154 MHz. In 1996, we introduced still faster versions of the processor with a cycle time of only 5.5 nanoseconds (182 MHz). Muskie also clearly shows its intended use in a commercial processing system rather than in a technical workstation.

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⁶At the time these processors were announced, they were given numbers rather than names. For example, the Muskie processor was given the very unimaginative identifier, A30. Because the processor code names are so much better, we are going to drop all references to numbers and use the code names for the AS/400 processors.

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Even though Muskie is not our latest PowerPC processor, it is worth spending some time looking at its design to understand the differences between a processor designed for commercial processing and a processor designed for technical computing. We then can understand why the decision was made to have Rochester concentrate on commercial processors for both the AS/400 and the RS/6000 and to have Austin concentrate on processors for technical computing.

The implementation of Muskie is a single-module, multichip, pipelined, superscalar design intended for the original high-end AS/400 RISC models. It is the only multichip implementation in the PowerPC family. This processor is a 4-way superscalar design, which means that a single processor can dispatch and execute up to four instructions per cycle. This implementation also supports multiprocessor configurations.

With all of its support circuitry, the Muskie implementation uses a total of seven chips that are packaged on a single multichip module with a total of more than 25 million transistors. One chip is an I/O control unit that is technically not a part of the processor. The other six chips that make up the processor complex, along with the interconnections between the chips, are shown in Figure 2.4.

Figure 2.4  Muskie Processor Block Diagram

Single-chip processors use CMOS (Complementary Metal Oxide Silicon) technology. CMOS consumes less power than other technologies, meaning it dissipates less heat. As a result, more transistors can be packaged on a single chip. As long as all circuits are contained on a single chip, the low-power circuits in CMOS are very fast. Going off the chip is another matter. Performance is reduced when CMOS drivers are used between chips in a multichip processor.

The technology used for all six chips in Muskie is BiCMOS (Bipolar-CMOS). Bipolar is a high-performance, high-power-consuming technology. Bipolar chips cannot be made as dense as CMOS chips because of the heat they dissipate. They have the advantage of being able to maintain their high speed between chips. BiCMOS is a technology that allows both CMOS and bipolar circuits on a single chip. The CMOS technology is used for the logic that is internal to the chip and the bipolar technology is used for the off-chip drivers.

BiCMOS is an excellent technology to use for a multichip processor. (Another familiar processor in the industry that uses a multichip BiCMOS implementation is the Intel Pentium Pro. This processor is packaged on a two-chip module and uses BiCMOS for the same reasons that Muskie does.) The downside of BiCMOS is higher heat dissipation. A more detailed look at the processor chips will help to explain why so many transistors are used for this implementation.