Another characteristic of the PowerPC architecture that is different from a conventional RISC processor is the use of several compound instructions. The biggest drawback of RISC relative to CISC is code expansion. A RISC processor takes more instructions than a CISC processor to perform the same program. Compound instructions reduce that code expansion. Some compound instructions are fairly simple, such as updating the base register on loads and stores, which eliminates the need for a separate add instruction. Others are more involved, such as load-and-store multiple instructions to allow several registers to be moved with a single instruction. There are also load-and-store string instructions, which load or store arbitrarily aligned byte strings. CISC fans will recognize this last pair of instructions as a not-very-carefully-disguised move-character instruction.

RISC purists objected and accused the PowerPC architects of selling out to the forces of CISC. In fact, the architects were simply recognizing that, in the real world, certain operations such as moving unaligned byte strings occur frequently enough that they need to be optimized in some way. If a compound instruction does the job, but in doing so violates some unwritten rule of RISC purity, so be it. Compound instructions do not signal a return to CISC architectures. They do, however, show that nothing is ever black and white.

These characteristics of aggressively exploiting superscalar capabilities and using compound instructions show the design philosophy of the PowerPC architecture. Other designs, such as the Sun SPARC and the Motorola 88110, also follow this philosophy. Some in the industry argue that the added complexity makes it difficult to achieve high clock rates, which are usually measured in megahertz (MHz). They believe higher performance can be achieved by exploiting clock rates rather than aggressive instruction-level parallelism.

What is a MHz? In recent years, MHz has become a popular way to specify the performance of the processor chip in a computer. An easy way to think of MHz is to relate it to the revolutions per minute (RPM) of an automobile engine. RPM is a measure of how fast the engine is spinning, or just how many revolutions of the crankshaft occur in a minute. A processor’s speed can be specified in terms of the number of cycles it can execute in a second. In one cycle, a processor can typically execute one simple instruction, so this sometimes is used as an approximation of the number of instructions that a processor can execute in a second. A hertz (Hz), named after a German physicist, is equal to one cycle per second. One MHz is equal to one million cycles per second.

Some examples that apply this high-clock-rate philosophy are the Digital Alpha, the HP PA-RISC 1.1, and the MIPS R4000 architectures. To illustrate the difference, let’s look at the PA-RISC 1.1 architecture. A PA-RISC 1.1 processor can typically dispatch two instructions per cycle. The smaller PowerPC processors dispatch three instructions per cycle, while the high-end models can dispatch four or more. This added parallelism gives the PowerPC a throughput advantage but at the cost of added complexity, which can slow the clock rate.

The debate over which is the best design philosophy continues. The two camps have been called “Speed Demons” (high clock rates) and “Brainiacs” (complexity). The point here is that the clock rate, measured in MHz, does not always indicate the performance of one processor compared to another. A 150 MHz Brainiac may easily outperform a 300 MHz Speed Demon. It all depends on the program being executed and the amount of instruction parallelism the compiler is able to exploit.

Some recent industry announcements may indicate that the scales are tipping in favor of a Brainiac design such as the PowerPC. In 1996 HP announced its next-generation architecture, which it dubbed PA-RISC 2.0. It appears that HP has succumbed to the siren call of complexity with the new processors having a 64-bit Brainiac design. Because PA-RISC 2.0 is still a processor-centric architecture, HP stated that it will be three to five years before 64-bit applications are available for the new hardware.