Many of the architecture changes we needed would be difficult to incorporate into the early versions of the PowerPC processors designed at the Somerset Design Center. At the high end of the AS/400 line, we needed processors that could handle massive amounts of data, and very wide data buses were needed to accomplish this throughput. We didn’t even consider trying to extend the 32-bit designs. It was doubtful that we could extend the early single-chip 64-bit design being developed at Somerset (it would later become the 620) because it was not sufficiently dense to package the size processor we needed at the high end of our line. We would have to build a multichip version of the architecture. Even at the low end of the AS/400 line, it was not clear what to use. We briefly proposed an extension to the 64-bit Somerset design 620 for our low end that we dubbed the 621, but eventually we concluded it would be easier to develop the AS/400 processors within IBM.

At the same time, the RS/6000 developers also concluded they could not use the early PowerPC processors in their high-end systems. The single-chip Somerset designs were okay at the low end, but a multichip design was required for their high-performance products. Besides, they wanted to incorporate some features, specifically for numerically intensive computing (NIC), that would support the high-performance technical computing marketplace. Many of these NIC features would not be found in the general PowerPC. They created an extension to the original POWER design that they called POWER2. The POWER2 design added more pipelines and new computational instructions. The first POWER2 design appeared in an RS/6000 in 1993.

The POWER2 processors were also used in the IBM Scalable POWER parallel System (SP2). The SP2 was IBM’s entry into the parallel processing computer market. The SP2 can have a large number of these processors all operating in parallel. This type of parallel machine is very good for certain kinds of engineering-scientific applications as well as for some commercial applications, such as scanning huge databases.

The AS/400 and RS/6000 architects initially wanted to achieve a common processor design. We decided to include in the Amazon architecture all of the extensions required for both the AS/400 and the RS/6000. In this way, a single common processor could be built sometime in the future that could support the special needs of both systems.

The first common PowerPC processor that we planned to use for both the AS/400 and the RS/6000 had several names. The RS/6000 people often called it the PowerPC 630. Internally, we named it Belatrix. Belatrix is a star in the constellation Orion. Few people know that this star is also called the Amazon Star. Belatrix was to be the star of the Amazon architecture.

As with many early designs, the Belatrix project was overly ambitious, trying to be everything to everybody on too short a schedule, and it was terminated. We had decided that it made more sense to have different versions of the PowerPC processors, optimized for various computing environments. Every PowerPC processor would implement a base set of instructions and functions. Beyond this base set would be extensions that could be optionally implemented for each processor.

Rochester would design the first 64-bit PowerPC processors with extensions for the commercial environment. We would use these processors exclusively in the AS/400. Later, the decision was made to use a later generation of 64-bit PowerPC processors designed in Rochester in both the AS/400e series and the RS/6000 starting in 1997.

With Belatrix gone, Austin began working on a new version of the 630, a 64-bit PowerPC design that would provide the NIC performance needed for future systems. In Rochester, we, too, started work on our version of Belatrix, which would become a follow-on PowerPC processor for the AS/400e series in 1998. Because Belatrix was named after a star, and Minnesota is known as the North Star state, we selected the name Northstar⁴ for our new processor.

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⁴This is not the first time we have used this code name. The System/32 was the North Star system before it was announced in 1975. This time around, we made it into a single word.

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The software picture using PowerPC that we took back to Kuehler looked much worse than the hardware picture. All application software and all system software that was above the MI was protected because of the AS/400 architecture’s technology independence. However, because PowerPC was so very different from the IMPI, the microcode written below the MI would have to be converted to the new processor. Automated tools could help port some of it to the new hardware. Still, a lot of this low-level operating-system code was dependent on the IMPI, and a large amount would have to be rewritten — a major undertaking. Because we needed our existing development programmers to deliver new releases of the AS/400, we estimated that several hundred new system programmers would have to be hired to do the work on the RISC-based systems.

Finally, there was the problem of schedule. We had originally planned to ship the new C-RISC processors in mid-1994. We had already started to work on these processors for the Advanced Series. If we used PowerPC, we would have to slip the schedule for the RISC processors into 1995. It would take us that long to build the processors with the extensions we needed and to rewrite the internal code. We would have to ship the Advanced Series with the IMPI processors and ensure that they could be upgraded to the PowerPC processors when they were available.

In early July of 1991, we went back to Kuehler with our results. Most in Rochester thought he would thank us for a good job, conclude that moving to the PowerPC processor was just too expensive, and send us back to build C-RISC. He didn’t. He gave us the green light and provided the development resources to make the move happen. Suddenly, we had to totally change both our hardware and software directions for the Advanced Series.

By the end of July, we had reorganized the laboratory to concentrate on the new system. The design of our first-generation high-end processor, which we called Muskie, was Rochester’s responsibility. This processor was to be a multichip implementation that could satisfy the demanding needs for very large commercial computers. The design for the low end of the AS/400 line went to the IBM laboratory in Endicott, New York. This line was called Cobra and was to be a single-chip, full 64-bit design.