Unfortunately, the research project was canceled before Cocke had the opportunity to prove his ideas. Then in 1976, at IBM’s Yorktown Research Laboratory in New York, he received another chance. He was authorized to design and build a high-speed telecommunications controller. Code-named the 801 after the building in which Cocke worked, this computer has generally been regarded as the first RISC computer. The 801 showed that compilers could take over the scheduling of a pipelined processor. The combination of a compiler that produced an instruction stream optimized for a specific pipelined processor and a simplified load/store processor similar to the original Cray machine was almost unbeatable.

Today’s RISC processors use Cocke’s idea of an optimizing compiler mated to the processor hardware. Advances in both hardware and compiler technologies contribute to the overall performance of a RISC processor. Because so many advances have been made in compilers in the past few years, some in the industry have suggested renaming RISC to “Relegate Interesting Stuff to Compilers.”

The first IBM product to use a descendant of the 801 was the PC RT. The office products division in Austin, Texas, needed a new processor and used the 801 as a starting point. A new microprocessor, called ROMP (Research/Office Products Microprocessor), incorporated a subset of the 801 to keep costs down. The chief architect and development manager for the PC RT was Glenn Henry. After we announced and shipped the System/38, Glenn, who was our programming manager, moved to Austin to lead IBM’s first RISC effort.

The 801 was also used as a base for RISC processors other vendors developed. In the early 1980s, research projects were in place at both the University of California at Berkeley under David Patterson and at Stanford University under John Hennessy. Patterson was the one who coined the term RISC. Both universities had graduate students who had worked at IBM Research and knew about the 801. The SPARC microprocessor used by SUN came out of Patterson’s project and the MIPS microprocessor came from Hennessy. Meanwhile, at nearby HP, Joel Birnbaum was leading the effort to design HP’s PA-RISC architecture. Birnbaum had managed the 801 group in IBM Research before going to HP. Thus, PA-RISC also had its origin in the 801 project.

These early RISC processors used a single pipeline, as did the original 801. Cocke and others in IBM reasoned that it should be possible to dispatch multiple instructions to multiple pipelines each cycle from a conventional linear instruction stream, thereby increasing performance even further. They called this a superscalar machine. The first superscalar RISC processor appeared in the IBM RS/6000 in 1990.

To identify this superscalar enhancement to a RISC processor, IBM named the architecture POWER for Performance Optimization With Enhanced RISC. The POWER architecture was also based on the 801. This architecture was the starting point for the joint effort between Apple, IBM, and Motorola.

To meet the future needs for all three corporations, certain modifications to the POWER architecture were required. Most POWER processors use multichip implementations. Some simplifications were made to the architecture to enable the building of low-cost, single-chip implementations (i.e., microprocessors). The POWER architecture did not support multiprocessor systems, so these features had to be added. New features were also added to support anticipated future applications. Finally, the 32-bit architecture of POWER was extended to include 64-bit addressing and operations. The changes resulted in the new PowerPC architecture. Figure 2.2 shows the evolution from the 801.

Figure 2.2  Evolution of PowerPC

IBM and Motorola, with help from Apple engineers, created a new design center to develop future PowerPC microprocessors. The Somerset² Design Center, located in Austin, was staffed primarily by Motorola and IBM engineers. Late in 1995, it was announced that Somerset had become part of IBM’s Microelectronics Division. Both Motorola and IBM are free to manufacture and market the processors designed at Somerset. Apple, for example, buys PowerPC chips from both IBM and Motorola. Motorola’s PowerPC processors are built in its Austin manufacturing facility. IBM manufactures its PowerPC chips in Burlington, Vermont.

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²Those readers who remember King Arthur may recognize Somerset as the mythical place warring factions went to make peace.

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It is important to note that in just the past couple of years the advances in RISC processor designs have been tremendous. Just about every RISC vendor, including the PowerPC consortium, has shipped a 64-bit RISC processor with on-chip hardware to do dynamic scheduling and branch prediction. The dynamic scheduling hardware on these chips uses the Tomasulo algorithm described earlier. Isn’t it amazing that we have now come full circle? Today’s processors have re-incorporated all the hardware RISC was originally envisioned to eliminate. Seymour Cray would be proud. The hardware designs he pioneered in 1964 have won over the simpler designs of the early RISC processors. These are definitely not your father’s RISC processors!