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Figure 2.1a Pipeline Scaler Processor — Five-Stage Instruction Pipeline
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Apple Computer in early 1991 was looking for a new processor for its future computers and believed that the future for PC processors was a RISC design. The PC processors that came from Motorola, Intel, and other vendors were still CISC designs. Up until that time, Apple had bought its processors from Motorola; and although Motorola had produced a RISC processor, it was not a big commercial success.
RISC technology offers fundamental advantages over the CISC designs — a RISC processor provides a performance advantage in a chip that is physically smaller and consumes less power. Apple recognized that the industry would eventually move in this direction, but in 1991 the available microprocessors were still predominantly CISC designs.
At the time, IBM had one of the industry’s best RISC processors in its RISC System/6000 (RS/6000). These processors were all multichip, 32-bit designs, but IBM had plans to announce a single-chip version in early 1992 (called RSC for RISC Single Chip). Hearing about Apple’s search for a new RISC microprocessor, IBM decided to make a sales call at Apple. Would Apple like to use RISC microprocessors from IBM?
After the shock wore off of having IBM, a competitor in the PC business, try to sell processors to Apple, Apple began to think maybe this was not such a bad idea. The company knew that Motorola also was looking at a new RISC design, and it suggested that the three companies get together. IBM agreed and discussions began. In September 1991, the three companies officially announced an alliance to jointly pursue the development of several exciting new technologies, including a broad family of microprocessors. The microprocessor design would be based on the RSC. They named the new family PowerPC.
The three partners recognized that market success depends on selling lots of these chips and having a large installed base of software. Thus, they began recruiting hardware and software vendors — including Toshiba, Canon, Zenith Data Systems, Harris Computer, and Groupe Bull, to name a few — to use PowerPC. To further increase the volume of processors sold, they also recruited companies outside the computer field. A good example is Ford Motor Company. In the future, Ford vehicles will use PowerPC microprocessors to perform functions from engine management to braking system control.
John Cocke at IBM Research developed the concepts of RISC. Cocke recognized that compilers had advanced to the point at which it was possible to simplify the instruction set of a processor and to let the compilers absorb much of the complexity that previously had been put into the hardware. His ideas were first embodied in a machine called the IBM 801 minicomputer. The PowerPC processors are direct descendants of the 801.
CISC designs had been primarily motivated by a desire to reduce the semantic gap between the binary machine level of the processor and the high-level languages (HLLs) that programmers use. Instructions were added at the binary machine level to match HLL instructions. The idea was that the processor would execute fewer of these complex instructions and save memory space. Unfortunately, the instructions at the binary machine level became so complex that microprogramming had to be used for almost every processor design. The overhead of the microprogrammed emulator slowed down the execution of frequently occurring simple instructions. Cocke reasoned that if only simple instructions were used, there would be no need for microprogramming. The hardware could directly execute all instructions. Further, if memory cost was not an issue, the compilers could generate the code for the more complex functions directly in-line. Memory sizes would increase but so should performance.
The 801 processor design came from the world of supercomputers. Supercomputers are the fastest computers available. Although the name supercomputer did not appear until the middle of the 1970s, there have always been designers willing to push the limits of hardware technology to create the fastest computer of the day. The name synonymous with supercomputers is Seymour Cray. Today’s RISC processor designs owe much to the pioneering efforts of this man.1
1Sadly, Seymour Cray, the Father of Supercomputing, died in October 1996, as a result of injuries suffered in an auto accident. He began designing computers in 1950 at Engineering Research Associates, a Minnesota company, and there developed the world’s first commercially successful scientific computer, the ERA 1103. In 1957, Cray was among the founders of Control Data Corporation. His designs for the 6600 and 7600 computers set new standards for the industry. In 1972, he founded the first of his own companies, Cray Research, where he built the world’s highest performance, general-purpose supercomputers. The legacy he left for all of us in the computer business will live on.
The single most important invention that enabled greatly improved performance in processors was pipelining. Pipelining, used for many years to implement micros to mainframes, is an implementation technique whereby portions of multiple sequential instructions are executed concurrently in various stages of the hardware pipeline. The first general-purpose computer to use pipelining in 1961 was the IBM 7030, which was also called Stretch. Figure 2.1a shows an example of a five-stage instruction pipeline. Each stage performs a specific function in the execution of an instruction. The time required for each stage to complete is called the processor cycle time.
Figure 2.1a Pipeline Scaler Processor — Five-Stage Instruction Pipeline
Figure 2.1b shows a timing sequence for the five-stage pipeline. During the first processor cycle, the stage 1 hardware fetches instruction number 1 from an instruction buffer. During the second processor cycle, the stage 2 hardware decodes instruction number 1 and fetches the contents of any needed registers. During this same cycle, the stage 1 hardware fetches instruction number 2 from the instruction buffer. At this moment, we have two separate stages working concurrently on parts of two separate instructions. This is a form of parallelism, and pipelined processors achieve their improved performance because of this parallelism. Note that we are assuming some other hardware in the processor is continuously keeping the instruction buffer full.
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Figure 2.1b Timing Sequence Example
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