Table of Contents


Index

32-bit PowerPC architecture, 26, 33
48-bit address, 179, 183, 201
64-bit address, 180, 201
64-bit PowerPC architecture, 25, 26, 34
64-bit RISC
processors, 2
technology upgrade, 10
65-bit processor, 32–33
96-bit address, 206

A

A Programming Language (APL), 359
Abbreviated virtual page number (AVPN), 215
Abstraction
levels of, 3–5
principle, 3
Accelerated Strategic Computing Initiative (ASCI), 44
Blue Mountain, 44–45, 335, 347
Blue Pacific, 44, 45, 47, 313, 335
Option Red, 44
Access groups
defined, 222
member directory, 223
process (PAG), 205
segments, 222–223
for temporary segments, 223
TOC, 223
Activation Group Directory (ActGrp Directory), 243
Activation groups
control information, 241
defined, 70
ILE, 243–244
naming, 241
Parent (PAGP), 241
Add Numeric (ADDN) instruction, 85, 86
ADDPFTRG (Add Physical File Trigger) command, 136
Address translation, 206–220
overview, 209–213
steps (tags active), 209, 211
steps (tags inactive), 212
virtual-to-real, 213–220
Addresses
48-bit, 179, 183, 201
64-bit, 180, 201
96-bit, 206
direct store, 189, 210
effective, 184–185
EPA header, 112–113
IOBU, 276
MI pointer format, 204
relative, 144
running out of, 205–206
segment header, 110–111
virtual, 200, 206
Advanced 36, 38, 61–62, 371
Advanced Micro Devices (AMD), 327
Advanced peer-to-peer networking (APPN), 274, 283
Advanced program-to-program communications (APPC), 274, 283
Advanced Unit Record Systems (AURS), 357
All-in-One, 348
Amazon architecture, 34
defined, 24
instructions, 33–34
American Standard Code for Information Interchange (ASCII), 99
Anderholm, Ferd, 351
Apache processor, 39–41
block diagram, 40
chip, 39
defined, 39
Mako box, 40–41
memory data switches, 45
memory subsystem design, 39
Millennium box, 40
physical packages, 39
PowerPC architecture implementation, 39
See also AS/400 processors
API-centric architecture, 8–9
Apple/Motorola PowerPC alliance, 23–24
Applets, 299
Application
enablement, 299–309
software, 5
technologies, 342–343
Application programming interfaces (APIs), 8, 161
definition work, 9
forms of, 8
interface, 9
ODBC, 171, 296, 308
POSIX, 8–9
sets, 9, 64
SPEC1170, 9
for writing applications, 49
Architecture, 2–3
Amazon, 24, 33–34
API-centric, 8–9
classification, 8–10
components, 3
defined, 2
high-level machine, 9–10
IMPI, 12, 21
instruction-set, 3, 4
Intel Pentium Pro, 6
multiple implementations of, 3
PA-RISC, 31
POWER, 20, 23
PowerPC, 20
processor-centric, 8
See also AS/400 architecture
Armstrong, Bill, 54
Artificial intelligence (AI) algorithms, 139
AS/400
in 21st century, 321–349
Advanced Entry, 39, 264
Advanced Series, xxxiv, 27, 31, 39, 378
Advanced Server models, 308
announcement of, 372
continual development work, 372
evolution of, 373
history of, 351–378
investment areas for e-business, 286
Java for, 300–303
PC attachment to, 171–172
tasking structure patent, 226
technology independence of, 226
Version 4 enhancements, 285–287
AS/400 architecture, 1
advanced-application, 10
function split, 51
philosophy, 9
See also Architecture
AS/400e series,
e-server models, 308–309
entry server, 39, 264
high-end growth for, 311–316
I/O, 46, 263–267
name, 376–378
operating system versions, xii
price/performance (P/P) improvements for, 316–319
processors for, 13, 26, 34, 39–41
See also AS/400
AS/400 processors, 34–41
48-bit address, 179
64-bit “industrial strength,” 48
Apache, 39–41
Cobra, 37–39
fifth-generation, 322–325
first-generation, 34–39
fourth-generation, 41, 313, 323
Muskie, 34–37
Northstar, 26, 41, 311, 323
numbers, 34
second-generation, 37–39
third-generation, 39–41
See also Processors
Assembler
defined, 3–4
for optimizing program, 5
Assembly language, 3
Asymmetric multiprocessing (ASMP), 236–237
defined, 236
design, 236
See also Symmetric multiprocessing (SMP)
Asynchronous Transfer Mode (ATM), 290
Atanasoff, John, 353–354
Atlas computer, 180
Authority, 163, 165–166
add, 165
adoption of, 167
ALL, 165
authorization list management, 165
CHANGE, 165, 169, 171
defined, 158
delete, 165
EXCLUDE, 166, 171
grouping, 167–168
limiting, 100
object, 99, 165–166
object existence, 165
object management, 165
object operational, 165
read, 165
special, 166
update, 165
USE, 165
Authority search algorithm, 169–171
illustrated, 170
implementation of, 169
search order, 169–170
speeding up, 171
Authorization list, 167
illustrated example, 168
implementation of, 167
See also Authority
Auto storage segments, 243
Automatic storage area, 238
Auxiliary storage directories, 223–224
Auxiliary storage pools (ASPs), 220–221
defined, 221, 315
disk failure and, 221
first, 221
Independent (IASP), 315–316
system, 316
user, 221, 316
Available message queue (AMQ), 277

B

Bains, Dick, xxix–xxx, 55, 124, 364–365, 370
Batalden, Glenn, 292
Behrens, Lou, 292
Belatrix, 26, 323
Benchmark programs, 344–345
SPEC, 344
TPC, 344–345
See also Performance
Berg, Bill, 25, 28, 54
Berry, Clifford, 353
BiCMOS (Bipolar-CMOS), 35–36
Binary numbers, 3
Binary radix trees, 149–155
binary representation, 151
building, 152
defined, 150
example illustration, 153
implementation of, 154–155
inserting entries in, 154
internals, 154–155
keys, 154
nodes, finding next, 154
removing entries from, 154
subdividing, 155
terminal node, 152
test node, 152
See also Machine indexes
Binary searches, 148–149
Binding
early, 70
late, 69
Birnbaum, Joel, 20
Bits
combination in bytes, 90
defined, 3
ECC, 196, 198
flag, 110
mode-control, 215
MSR, 207–208
page-protection (PP), 219
parity, 197
tag, 31–32, 198–199
Booth, Dick, 332
Bound by reference calls, 70–71
Bound to copy calls, 70
“Brainiacs,” 31
Branch (B) instruction, 85, 86
Branching
four-way, 84
prediction, 18
Bring, 146, 190
Bring up Binds (BUBs), 56
Bundling, 52
Bus control table (BCT), 277
Bus control unit (BCU), 267
function of, 268
at IPL time, 269
Bus unit block (BUB), 277, 279, 280
Buses
I/O, 261, 262, 263
memory, 261
OPEND message, 281
OPSTART message, 280–281
PCI, 262, 263, 264
SAN, 266
SPD, 260, 261, 263, 267–270
Byte code, 299–300

C

C++ programming language, 7, 55–56
C2 level security, 162–163
certification, 162
defined, 163
See also Security; System security levels
C programming language, 7, 56
Cache affinity, 235, 236
Cache snooping, 46, 333
Cache-coherent NUMA (CC-NUMA), 332–336
example, 334
RAD, 334
remote cache, 335
servers, 333
Cache-only memory architecture (COMA), 332–336
implementations, 335
local node main memory, 335
simple (S-COMA), 335–336
Caches
Cobra, 38–39
data (D-Cache), 28
defined, 28
hierarchy of, 42
instruction (I-Cache), 28
large, 42
Call bound procedure (CALLB) instruction, 71
Call external instruction, 69
Call program (CALLPGM) instruction, 71
Call stack, 167
Capability, 99
CDC 6600, 17, 18, 283
Central Electronics Complex (CEC), 317
Channels, 262
System/38, 262
System/370, 262
CHGCMD (Change Command) command, 173
CHGQRYA (Change Query Attributes) command, 119
Chili pepper rating system, xxxviii
Classes, 54
Client Access, 96, 297
enhancements, 298
product composition, 297–298
for Windows 95/NT clients, 298
Client/server
characteristics, 296
computing, 296–299
defined, 296
model, 22
model simplification, 297
Clusters, 314–316
CMOS (Complementary Metal Oxide Silicon) technology, 35
Cobra processor, 27, 37–39
caches, 38–39
clock rates, 38
Cobra-0 version, 38
Cobra-4 version, 38
Cobra-CR version, 38
Cobra-Lite, 38, 61
defined, 37–38
design objective, 38
instructions, 38
Muskie vs., 38
versions, 38
See also AS/400 processors
Cocke, John, 15–16, 19–20, 362
Codd, E.F., 124–125
Collaborative computing, 294–296
Commercial Processing Workload (CPW), 345
Commercial-RISC (C-RISC), 23, 27, 206
Commit block, 147
COMMIT operation, 135
Commitment control, 134–135
defined, 135
in SLIC, 147
Common Gateway Interface (CGI), 290
Common intermediate form, 67
Common Object Model (COM), 300
Common Object Request Broker Architecture (CORBRA), 301–302
Common Programming APIs (CPA), 256
Common Use Back End 1 (CUBE-1), 69
Compilers
AS/400 language, 67–71
CUBE-3, 71
defined, 4
EPM, 68
EPM on V4 RISC, 73
front end, 66
HLL, 75
ILE program model, 71, 72
OPM, 68
OPM on V4 RISC, 73
optimizing, 65–66
RISC, 327
VLIW, 326
Complex instruction set computer (CISC) processor, 1, 2
Component Specific Exception Handlers (CSEHs), 248
Components, 62
separate, 12
See also Integration
Componentware, 299
Computer architecture. See Architecture
Conferencing, 294–295
Connection control block (CCB), 277
Conte, Paul, 126
Context switching, 248–250
Control address table (CAT), 277
Control blocks, 276–277
available message queue (AMQ), 277
bus control table (BCT), 277
bus unit block (BUB), 277, 279, 280
connection, 277
control address table (CAT), 277
illustrated, 276
local connection, 277
process, 146, 241
remote connection, 277
request response (RRCB), 278, 280
Control Data Corporation, 16, 17
Control Storage Processor (CSP), 60, 262
Controller description (CTLD), 270, 275
Copy Bytes Left-Adjusted with Pad (CPYBLAP) instruction, 86, 87
Corrigan, Mike, 24
CPU. See Processors
Cray, Seymour, 16–19, 21, 283
Cray CS6400, 312
CREATE instruction, 107, 109
CRTDUPOBJ (Create Duplicate Object) command, 146
CRTLF (Create Logical File) command, 127, 129
CRTPF (Create Physical File) command, 127, 128
CUBE-3, 71
Cursors, 144–145
defined, 144
permanent, 146
segments, 145
temporary, 146
uses, 144–145
Cycle stealing, 261
Cyclic redundancy check (CRC), 199, 318

D

Dahl, Steve, 58
Data
analysis tools, 121–122
capabilities, 310–311
description, 127–130
independence, 130–132
informational, 117–118
pointers, 103
propagation tools, 118, 140–141
rates, 339–340
security, 132
sharing, 132
user’s path to, 145–146
Data cache (D-Cache), 28
Data Description Specification (DDS), 125
attribute definition, 127
interface, 125, 126
record/field names, 126
Data dictionary, 129–130
defined, 130
purpose of, 130
Data integrity/recovery, 133–138
commitment control, 134–135
high-availability disk systems, 136–138
journaling, 133–134
referential integrity, 136
SMAPP, 134
triggers, 135–136
Data mining, 116
defined, 122
tools, 122
Data spaces, 143
indexes, 143–144
records, 143
segments, 143
Data warehousing, 116, 117–122
defined, 118
EIS/DSS tools, 121–122
managing, 122
multidimensional databases and, 119, 120–121
parallel processing, 119–120
propagation tools, 118
warehouse components, 118
warehouse refreshment, 118
Database Design and Programming for DB2/400, 126
Database functions, 142–147
commitment control in SLIC, 147
cursors, 144–145
database objects, 142–143
data-space indexes, 143–144
SLIC journaling, 147
user’s path to data, 145–146
See also Databases
Database management system (DBMS), 125
defined, 125
functions, 127
Database objects, 142–143
Database operations, 126–142
data description, 127–130
data integrity/recovery, 133–138
data security, 132
data/program independence, 130–132
database performance enhancements, 139
DataPropagator, 140–141
distributed databases, 139–140
file creation, 127–130
gateways to other databases, 140
national language support, 138–139
OptiConnect, 141–142
predictive query governor, 139
stored procedures, 138
Database servers, 118–119
Databases, 116
distributed, 139–140
evolution of, 122–125
gateways to, 140
index, 123
integration of, 116–117
interfaces, 126
journals, 133–134
key, 123, 144
multidimensional (MDD), 119, 120–121
records, 123
size supported by SLIC, 142
System/38, 116, 122–123
System/R operations, 124
See also DB2/400
DataPropagator, 140–141
Data-striping technique, 337
DB2/400, 116–117
challenges, 310
defined, 116
focus for, 310
naming, 117
parts of, 125
performance enhancements, 139, 310
See also Databases
Decision-support-system (DSS) tools, 121
Delete Program Observability, 79
Dequeuing, 231
Device description (DEVD), 270
Digital
Alpha architecture, 2
AlphaServer, 346–347
move to RISC, 2
VMS operating system, xxiii
Direct memory access (DMA), 269
Direct store address, 189, 210
Disk arrays, 337–338
Disk extents, 221–222
defined, 221
number of pages in, 221
using, 221–222
Disk management, 220–224
ASPs, 220–221
storage segments, 221–224
Disk mirroring, 137
Distributed Computing Environment (DCE), 255
Distributed Data Management (DDM), 140
local system, 272
OptiConnect, 141
Distributed databases, 139–140
Distributed Relational Database Architecture (DRDA), 140, 272
Distributed shared-memory machine, 43
Distributed System Object Model (DSOM), 256, 302
Ditzel, David R., 355
Document management, 294
Domino, 295–296
Doubleword, 198
Drums, 181
DSPJOBQ (Display Job Queue) command, 91
DSPOUTQ (Display Output Queue) command, 91
Dynamic priority scheduling, 237
Dynamic scheduling, 18

E

e-business,
definition, xxxvi, 287
investment areas for e-business, 286–287
Early binding, 70
Eckert, J. Prespert, 352–353
Effective address, 184–185
defined, 184
overflow (EAO) exception, 203
Effective segment identifier (ESID), 210–211
Electronic Data Interchange (EDI) applications, 305
Eligibility, 235, 236
Ellison, Larry, 291
E-mail, 294
Emulation, 4
Encapsulation, 54, 65, 90
ENIAC (Electronic Numerical Integrator and Calculator), 352–353
Enqueuing, 231
Enrolled, 159
EPA header, 107, 111–113
addresses, 112–113
attributes, 112
information, 111
object identification fields, 112
See also Headers; System objects
Error-correcting code (ECC), 196
bit, 196, 198
memories, 197
Events, 245–246
defined, 245
machine-related, 245
object-related, 245
Exceptions, 245–248
defined, 245
errors, 245
monitoring, 246
SLIC, management, 246–248
user-defined conditions, 245
Exchange, 190
Exclusive or (XOR) operation, 137–138, 154
defined, 137
example, 138
result of, 137
Executive information systems (EISs), 121
Exit program, 176
Extended Binary Coded Decimal Interchange Code (EBCDIC), 99
Extended Program Model (EPM), 67
compiler, 68
compiler on V4 RISC, 73
External file description, 130

F

Fess, Ron, 161
FFQRETSVRSEC system value, 159
File creation, 127–130
File Server I/O Processor (FSIOP), 305–306
File Transfer Protocol (FTP), 175, 176, 290
Firewalls, 176
First Level Exception Handlers (FLEHs), 248
Floating Point Systems (FPS), 328–329
Floating-Point Unit (FPU) chip, 36
Fort Knox, xxvi–xxvii, 368–370
Frameworks, 302
Persistence, 302
San Francisco, 304
Free space directory, 223
FS (Future Systems), 361–364
FS Machine (FSM), 363
Furey, Tom, xxxii, 125, 371–372, 375

G

Gates, Bill, 291
Gebhardt, Carl, xxxiv, 370
Gerstner, Lou, 13
Global File System (GFS), 339–341
future of, 341
at NAB, 340–341
Graphical User Interface (GUI), 341
Group profiles, 167–168
access to, 167
defined, 167
primary group, 168
See also User profiles
Groupware, 294–296
conferencing, 294–295
defined, 294
document management, 294
e-mail, 294
growth of, 294
products, 295
scheduling, 295
server components, 294–295
workflow, 295

H

Haines, Malcolm, xxxvii–xxxviii
Hansen, Pete, 371
Hardware abstraction layer (HAL), 307–308
Hardware context switching, 248–250
Hashing, 213–215
Headers
customized, 107
EPA, 107, 111–113
segment, 107, 109–111
Heap
list, 243
spaces, 243
storage area, 238
Hennessy, John, 20
Henry, Glenn, xxxi–xxxii, 19, 92, 364–365, 368
Heterogeneous element processor (HEP), 324
Hewlett Packard (HP),
HP 9000, 325, 348
Precision Architecture (PA), 2
High-availability disk systems, 136–138
High-end growth, 311–316
High-level languages (HLLs), 4, 75
High-level machine architecture, 9–10
Hoffman, Roy, xxix–xxx, 226, 319, 328, 364–365, 370
Horizontal Licensed Internal Code (HLIC), 53
Horizontal Microcode (HMC), 52
Howard, Phil, 154
HTML
Common Gateway Interface (CGI), 175
database tools, 174
defined, 174
gateway, 174, 289, 292
SQL commands with, 175
HTTP, 174

I

I/O, 259
adapter, 261, 262, 270
buffers, 94
buses, 261, 262, 263
components, 271–277
concepts, 260–263
control blocks, 276
costs, 317
devices, 261
expansion units, 46
future subsystem technology, 336–337
hardware structure, 265
industry-standard, 263–267
language of, 271
memory-mapped, 210
objects to support, 270–271
performance, 41, 312
processing, 263
request, 274, 275
request message (IORM), 278, 279
structure, 262, 273
subsystem, 46, 47
to/from a virtual page, 190
I/O bus unit (IOBU), 267, 268
addresses, 276
defined, 267
function of, 267
I/O operations, 8, 270–283
end illustration, 282
local, 282
start illustration, 278
I/O processors (IOPs), 119, 337
architecture, 263
functions, 305
LAN, 260
memory, 270
multifunction, 263
multiple, 260
PCI, 270
PowerPC-based, 266, 337
slave storage operation and, 269, 270
I/O system, 259–283
defined, 259
design methods, 260
in state of transition, 260–267
subsystem, 259
IBM
Advanced Unit Record Systems (AURS), 357
Fort Knox, xxvi–xxvii, 368–370
FS (Future Systems), 361–364
FS Machine (FSM), 363
General Systems Division (GSD), 362–363, 368
Haifa Research Laboratory, 69
Iliad, 369
microkernel, 58
Net.Commerce, 291
Network Station, 342
POWER architecture, 20
RS/6000, 15, 20, 317, 323
Silverlake project, 370–372, 376, 377
Stretch, 16
Superior, 378
System Application Architecture (SAA), 377
System Object Model (SOM), 301
System Products Division (SPD), 368–369
System/3, 59, 90, 356–359
System/32, 59–60, 360
System/34, 123, 360
System/36, 11, 58–62
System/38, 32, 52, 89, 364–366
System/360, 18–19, 356–357
System/370, 262, 361–363
System/390 Parallel Sysplex, 315
System/Q, 364–365
Workplace, 374–376
IBMLZ1 compression algorithm, 319
ILE activation group, 243–244
component definition, 243
illustrated, 244
See also Activation groups; Integrated Language Environment (ILE)
ILE optimizing translator (OX), 69, 72–73
ILE processes, 241–244
Activation Group (ACTGRP), 242
exception monitoring, 246
model, 239–241
Parent Activation Group (PAGP), 241
Process Activation Work Area (PAWA), 241
Process Control Block (PCB), 241
Process Queue Space, 243
structure, 241–243
tombstone segments, 242–243
See also Integrated Language Environment (ILE); Processes
ILE program model, 239
Iliad, 369
IMPI architecture, 187
defined, 21
defining, 365
extension of, 23
instruction set, 78
instructions, 21, 78, 199
interface, 21
op-code extenders, 78
Independent ASP (IASP), 315–316
Indexes
data-space, 143–144
defined, 123
machine, 147–155
Indicators, 85
Industry-standard I/O, 263–267
Information Management System (IMS), 125
Inheritance, 54, 90
Instances, 54
Instruction cache (I-Cache), 28
Instruction pointers, 103
Instruction sets
IMPI, 78
MI, 65, 67
See also Instructions
Instructions
ACTIVATE CURSOR, 145, 146
ADDN, 85, 86
Amazon, 33–34
B, 85, 86
call external, 69
CALLB, 71
CALLBP, 240
CALLPGM, 71, 240
COMMIT, 147
CPYBLAP, 86, 87
CREATE, 107, 109
DEACTIVATE CURSOR, 145, 146
DECOMMIT, 147
defined, 3
IMPI, 21, 78, 199
memory-to-memory, 18
MI, 64, 65
MI example, 85–87
ODT and, 81
OPM, 80
privileged, 166
REQIO, 274
RESOLVE, 101
RISC, 15
ROLLBACK, 147
tag, 198
Instruction-set architecture, 3, 4
Integrated file system (IFS), 96–99, 290
data format, 98
defined, 97
directories, 97
naming convention, 97
subdirectories, 97
Windows client view of, 98
Integrated Language Environment (ILE), 69
binder packages, 69
MI template, 71
program model compilers, 71, 72
See also ILE activation group; ILE processes
Integrated PC servers (IPCS), 176, 305–308
benefits, 306
in remote AS/400, 306
Integrated security, 158
Integration, 11, 62
flexibility and, 12
MI and, 11
Intel
IA-64 architecture, 325, 327
iAPX 432, 355
Merced, 325, 327–328, 331
microprocessing chips, 14
MMX extension, 63–64
Pentium II, 64
Pentium Pro, 6, 36, 42, 64
Pentium processor designs, 323
Interactive processing, 194
Interactive SQL, 126
Interface Definition Language (IDL), 301
Internal Microprogrammed Interface. See IMPI
Internet, 288
Internet Connection, 288
illustrated, 289
Secure Server, 290
Internet Message Access Protocol (IMAP), 288
Interoperability, 296
Interpretation, 4
Interprocess communications facility (IPCF), 275–276
data structures, 279
router, 281
router queue, 281
Interrupt handler, 228
Interrupts, 245
alignment, 247
classification of, 246
data storage, 247
decrementer, 247
defined, 228
direct-store error, 247
external, 247
floating-point assist, 247
floating-point unavailable, 247
instruction storage, 247
instruction-caused, 247–248
machine check, 246
performance monitor, 247
program, 247
system call, 247
system call vectored, 248
system reset, 246
system-caused, 246–247
trace, 247
Inverted page tables, 213
Investment areas, 286
Invocation work area (IWA), 239

J

Java, 299–303
applets, 299
for AS/400, 300–303
byte code, 299–300
class libraries, 299
cross-platform applications and, 301
defined, 299
Development Kit (JDK), 299
interpreted, 301
object model, 301
strength of, 300
Virtual Machine (VM), 299
Java Beans, 300
JavaStation, 293
Jobs
defined, 228, 251
description, 253
full-function, 256
routing steps, 251
structures, 253–254
work management and, 251–254
Join operation, 124
Jones, Chris, 28, 56
Journal data segment, 147
Journal ports, 147
Journal spaces, 147
Journaling, 133–134
defined, 133
journal entries, 147
SLIC, 147
support, 133
uses, 133–134

K

Kelly, Jim, xxxiii
Kempke, William, 226
Kernel
defined, 50
Mach, 57–58
SLIC technologies, 57–58
System/38, 52
Keys, 144
binary radix tree, 154
binary representation of, 151
defined, 123
Kilby, Jack, 354
Kiscaden, Dick, 359–360
Klotz, Ray, xxxi–xxxii, 202, 229, 360, 364–365
Kuehler, Jack, 23–24, 27

L

Late binding, 69
Libraries, 94–96
class, 55
defined, 94
name of, 95
QSYS, 95
structure, 94–95
Licensed internal code (LIC), 49–53
contents, 50
functions, 50
implementations, 50
Line description (LIND), 271, 275
Linus, 359–360
Local connection control block (Local CGCB), 277
Logical files
categories of, 128–129
creating, 128–129
format, 130
join, 129
multimember concept, 144
multiple-format, 129, 131
security, 132
structure, 128
Logical unit description (LUD), 270
Lookaside directory, 223
Loosely coupled parallel database system, 120
Lotus Notes, 295
Luick, Dave, 330

M

Machine indexes, 147–155
binary radix trees, 149–155
binary searches, 148–149
characteristics of, 148
defined, 148
uses, 148
Machine space pointers, 103
Machine State Register (MSR), 207–209, 249
64-bit mode bit, 207, 208
bit settings, 250
bits, 207–209
C2 security bit, 208
data relocate bit, 207, 208
defined, 207
instruction relocate bit, 207, 208
interrupt prefix bit, 250
problem state bit, 208
user state bit, 208–209
Main Store Control Unit (MSCU) chip, 36, 60
Massachusetts Institute of Technology (MIT), xxiii
Massively parallel processor (MPP), 43
configuration support, 120
systems, 43, 119
Materialization, 77–78
defined, 77
definition table (MDT), 114
Mattson, Paul, 54
Mauchly, John W., 352–353
McCullough, John W., 226
McNealy, Scott, 292
Megahertz (MHz), 30
Memory
access modes, 218–219
bus, 42
bus controller, 261
coherence, 218
data switches, 45
ECC, 197
interleaving, 45
IOP, 270
MI and, 76
model characteristics, 207
organizations, 43–44
performance, 41
pool, 253
protection, 196, 219–220
segmented, 105–106
sharing, 312
subsystem, 41–47
switches, 46–48
tags, 31
virtual, 105, 180–186
Memory-mapped I/O, 210
Memory-to-memory instructions, 18
Metadata, 122
Methods, 54
MI, 49–51, 360, 363
architecture overview, 64–65
AS/400, 75
boundary, 10, 64, 65
characteristics of, 71–76
code, 10
components, 64
containers, 65
conventional, 74
decimal rounding, 83
defined, 9
functions, 11
illustrated, 74
instruction examples, 85–87
instruction formats, 81–82
instruction set, 65, 67
instructions, 64, 65
integration and, 11
memory and, 86
objects, 64
as only external interface, 52
op-code, 82–84
op-code bit assignments, 83
op-code extender, 84–85
pointer address format, 204
pointers, 32
security and, 158
system objects, 76, 77, 91, 101–104, 105–114
MI programs, 76–79
creating, 76–77
destroying, 77
materialization, 77–78
observability, 79
template, 78, 79–87
See also MI
Microcode, 52–53
defined, 52
System/38, renaming, 53
Microkernels
64-bit multiuser, 375
defined, 226
function of, 227
Mach microkernel, 57–58, 228
technologies, 226–228
Microprocessors, 3
Microprogramming, 4
Microsoft
ActiveX, 298, 300
Common Object Model (COM), 300
NetPC, 293
Open Database Connectivity (ODBC), 171, 296, 308
Object Linking and Embedding (OLE), 300
Windows NT, preface, 192, 301, 307–308
MIPS microprocessor, 20
Module Binding Vector (MBV), 243
Modules, 70
Mondello, Tony, 370
Moore, Gorden, 13, 354–355
Moore’s Law, 13–14, 322
Multidimensional databases (MDDs), 119, 120–121
defined, 120
support, 121
Multifunction IOP (MFIOP), 263
Multimedia extension (MMX), 63–64
Multiprocessing
asymmetric, 236–237
symmetric, 37, 44–46, 235–236
Multiprocessors, 234–235
future of, 331–336
scalable shared-memory, 331–332
Multiprogramming, 181
Multipurpose Internet Messaging Extensions (MIME), 288
defined, 288–289
Secure (SMIME), 289
Multisegment objects, 107–109
Multithreaded processors, 324
Muskie processor, 34–37
BiCMOS technology, 35–36
block diagram, 35
chips, 35, 36
Cobra vs., 38
commercial optimization, 37
defined, 34
implementation, 34–35
instruction cache, 42
SMP configuration support, 37
speed of, 34
See also AS/400 processors
Mustain, Dick, 54, 58, 370

N

National language support, 138–139
Net.Commerce, 291
NetPC, 293
Network Computer Reference Profile, 292, 293
Network Computers (NCs), 172, 291
proponents of, 291
See also PCs
Network computing, 287–294
desktop, 291–294
Internet, 288
revolution, 287
standards implementation, 288–291
Web, 288
Network description (ND), 271, 275
Network File System (NFS), 340
Network interface description (NETINTD), 271
Network Station, 342
Network user interfaces (NUIs), 341–342
for IBM Network Station, 342
introduction of, 341
New Machine Interface (NMI), 361–362
Northstar processor, 26, 41, 323
See also AS/400 processors
Nonuniform memory access (NUMA) machines, 44, 332
cache-coherent (CC-NUMA), 332–336
implementations, 332, 333
name of, 333
Noyce, Robert, 354–355
Numerically intensive computing (NIC), 25

O

Object definition table (ODT), 105
components, 80
defined, 80
Direction Vector (ODV), 80
Entry String (OES), 80
instructions and, 81
Object Linking and Embedding (OLE), 300
Object Management Group (OMG), 301
Object-oriented (OO) programming, 54, 343
class libraries, 55
classes, 54
concepts, 54–55
encapsulation, 54
inheritance, 54, 90
instances, 54
methods, 54
native languages, 343
objects, 54
polymorphism, 55
problem with, 343
strength of, 56
technology, 343
Objects, 89–114
accessing, 99–103
authority, 99–100
authorization of, 163, 165–166
changing, 186
damage, 112
database, 142–144
data-space, 143
defined, 54
finding, 94–99
first use of, 89
I/O support, 270–271
libraries, 94–96
MI, 64, 65
MI system, 76, 77, 91
multisegment, 107–109
naming, 91–93
OS/400, 91
owned and authorized, 163, 165
permanent, 104
persistence of, 104
process control block, 146
program, 105
reasons for using, 90
in single-level store, 188
temporary, 104
Observability, 79
Offset
byte, 211
defined, 210
On-line analytical processing (OLAP), 121
Online transaction processing (OLTP), 115
Op-code extender, 84–85
Opel, John R., 361
Opel task force, 361
Open Database Connectivity (ODBC) APIs, 171
Operating systems
future technologies, 339
NetPC, 293
security, 162
working with conventional virtual memories, 193
Operations Navigator, 298
OPNQRYF (Open Query File) command, 146
OptiConnect, 141–142
clustering technology, 314
DDM, 141
defined, 141
implementation, 315
uses, 141–142
Optimizing compiler, 65–66
Order operation, 124
Original Program Model (OPM), 67, 239
block-structured language support, 69
compiler, 68
compiler on V4 RISC, 73
instructions, 80
program template, 69, 80
storage area support, 239
OS/400, 62
contents, 50
Distributed Database Directory, 140
Distributed Database Driver Manager, 140
functions, 50
future enhancements, 339
security, 162
OS/400 objects, 91
database file, 94
list of, 92
management, 99
one-to-many mapping, 93
one-to-one mapping, 91
See also Objects
OVRDBF (Override with Database File) command, 145, 146
OX, See ILE optimizing translator

P

Page faults, 189, 190, 215
defined, 42
non-database, 189
Page frames, 190–191
number of, 211
removing, 191
Page table entries (PTEs), 214, 215–218
first field in, 215
format, 216
length of, 215
not finding, 215
page-protection (PP) bits, 219
TLB holding, 217
Page table entry groups (PTEGs)>, 189, 214
number of, 215
universal distribution across, 215
Page tables, 192, 213
inverted, 213
See also Page table entries (PTEs)
Page-replacement algorithm, 217
Pages, 189
defined, 106
protection, 219–220
reference bits and, 189
Parallel processing, 119–120
PA-RISC architecture, 31, 325
Parity bit, 197
Password security, 160
Patterson, David, 20
PC Support, 96
PCs
attaching to AS/400, 171–172
integrated servers, 305–308
proponents of, 291
total cost of ownership (TCO), 292
See also Network Computers (NCs)
Pentium processors, 6, 36, 42, 64, 323
Performance
benchmark programs, 344–345
comparing, 345–347
database, 310
I/O, 41, 312
improvements, 316–319
interactive, 191
measuring, 343–344
memory, 41
process switching, 195
single-processor, 312
total system, 343–347
VLIW, 326
Peripheral Component Interconnect (PCI)
adapter cards, 263
bus, 262, 263, 264, 270
bus interface, 267
I/O card packaging, 267
IOPs, 270
move to, 317
transition to, 263
Permanent directory, 223
Permanent objects, 104
Persistence, 184
Phase, 65
Physical files
creating, 128
parts of, 128
security, 132
structure of, 130
triggers, 135–136
Physical security, 159
Pipelined processors, 16, 18
Pipelining
defined, 16
first computer use of, 16
PL/MP language, 55
Pointers, 195–206
capability, 99
corruption protection, 191
data, 103
hardware protection for, 196–198
inside, 200–201
instruction, 103
length of, 195
machine space, 103
memory space, 197
on disk, 199–200
procedure, 103
resolved, 201
space, 76, 102
structure, 196
system, 76, 99–101
types of, 101–103
use for, 200
Point-to-point protocol (PPP), 174–175, 290
Polymorphism, 55
Porting, 54
POSIX, 8–9, 97
process, 255–256
process model, 255
threads, 255
Post Office Protocol (POP) server, 288
Postfix, 80
POWER2 architecture, 26
POWER architecture, 20, 23, 212
PowerPC, 13–48, 373–374
630, 26
alliance, 14–15
software, 33
technology, 13–48
technology for AS/400, 23–28
PowerPC architecture, 20, 25, 28–34
32-bit, 26, 33
64-bit, 25, 26, 34
chips, 20
effective address, 184
evolution of, 15–21
extensions, 31–34
mode-control bits, 215
model, 29
tag register, 200
PowerPC processors, 13, 29
implementations, 29
IOPs, 337
third generation of, 313
Predictive query governor, 139
Price/performance (P/P) improvements, 316–319
commonality, 317
I/O technologies, 317–319
Privileged instructions, 166
Procedure Reference Table (PRT), 243
Procedures
defined, 70
invocation, 240
pointers, 103
Process access group (PAG), 205
Process control block, 146, 241
Process switching, 182, 193, 195
performance, improving, 195
use of, 195
Processes, 237–244
active execution environment, 255
defined, 228
ILE, 241–244
management of, 225–257
POSIX, 255–256
responsibility of, 237–238
support, 238
Processing Unit (PU) chip, 36
Processor-centric architecture, 8
Processors
64-bit Alpha, 7
65-bit, 32–33
801, 16, 19
chip circuits, 323
CICS, 1, 2
context, 249
cycle time, 16
defined, 3
fifth generation, 322–325
FPS, 328–329
future technologies, 322–331
HEP, 324
megahertz (MHz) rating of, 343
microprocessor, 3
MIPS, 20
multithreaded, 324
PA-RISC, 7
PC, 5
Pentium, 323
pipelined, 16, 18
POWER2, 26
POWER, 20
PowerPC, 29
RISC, 1, 2
ROMP, 19
SPARC, 20
stall cycles, 42
SuperSparc, 312–313
System/36, 11
VLIW, 326–327
See also AS/400 processors
Program
adoption of authority, 167
defined, 70
exit, 176
independence, 130–132
invocation, 238
objects, 105
Program Activation Control Block (PACB), 243
Program Automatic Storage Area (PASA), 239
Program Resolution Monitor (PRM), 67
Program Static Storage Area (PSSA), 239
Programming
assembly-level, 4, 5
high-level, 4
Project Lightning, 298
Projection operation, 124
Propagation tools, 118
Proxy, 302
Purge operation, 190–191
PWRDWNSYS (Power Down System) command, 166, 208

Q

QAUDJRL system value, 159
QMAXSIGN system value, 159
QRETSVRSEC system value, 159
QSECURITY system value, 159
QSYS library, 95
QTMHHTTP user profile, 175
QUEL language, 125
Query optimizer, 139
Queues
available message (AMQ), 277
send/receive, 233–234
task dispatching (TDQ), 231–232

R

Radin, George, 362, 369
Ranweiler, Jim, 316
RCVMSG (Receive Message) command, 234
Ready state, 230
Real page number (RPN), 211
data structure containing, 213
defined, 211
See also Virtual page number (VPN)
Reduced instruction set computer (RISC) processor, 1, 2
32-bit, 23
64-bit, 2
AS/400 commercial, 21–23
beyond, 325–328
commercial (C-RISC), 23, 27, 206
compilers, 327
Digital move to, 2
growth of, 311–314
instructions, 15
superscalar, 326
technology advantages, 15
Redundant arrays of inexpensive disks (RAID), 137
disk technologies, 306
technique, 137
Referential integrity, 136
Registers, 6
64-bit floating-point, 23
MSR, 207–209
segment, 184, 192
tag, 200
TLB, 189, 193
Relational databases, 122–125
Relative address, 144
Remote connection control block (Remote CGCB), 277
Remote-access device (RAD), 334
Report Program Generator, See RPG
Request response control block (RRCB), 278, 280
RESOLVE instruction, 101
Resolved pointers, 201
Resource security, 160–161
Reverse Polish, 80
Revolutions per minute (RPM), 30
Rice, Rex, 354
RMVPFTRG (Remove Physical File Trigger) command, 136
ROLLBACK operation, 135
ROMP microprocessor, 19
Rounding, 83
Routing steps, 251
RPG, 358
indicators, 85
RPG II, 358
RS/6000, 15, 20, 317, 323
Rubin, Richard, 180
Running state, 230
RVKOBJAUT (Revoke Object Authority) command, 173

S

San Francisco, 303–305
Advisory Group, 305
defined, 303
frameworks, 304
layers, 304–305
market for, 305
Scalable Coherent Interface Link (SCIL), 266, 336
Scalable shared-memory multiprocessors, 331–332
Scan, 123
Scheduling
dynamic, 18
dynamic priority, 237
groupware, 295
Schleicher, Dave, 375–376
Schmidt, Bob, 59
Schneider, Pete, 362
Schwartz, Steve, 371, 378
Searches
authority search algorithm, 169–171
binary, 148–149
TLB, 217
Second Level Exception Handler (SLEH), 248
Secure Electronics Transaction (SET), 176, 291
Secure Multipurpose Internet Messaging Extensions (SMIME), 289
Secure Sockets Layer (SSL), 176, 290
Security, 157–177
administrator, 164
C2 level, 163
data, 132
implementation, 158
importance of, 176–177
integrated, 158
MI and, 158
network computing and, 171–176
no, 159–160
officer, 164
operating system, 162
password, 160
PC clients and, 171–172
physical, 159
resource, 160–161
viruses/worms/Trojan horses and, 172–174
Web serving, 174–176
See also System security levels
Segment header, 107, 109–111
addresses, 110–111
flag bits, 110
information, 109
See also Headers; System objects
Segment identifier (SID), 202
effective (ESID), 210–211
extenders, running out of, 205
temporary, 205
virtual (VSID), 210–211
wrap, 205
wrap problem, reducing, 206
Segment look-aside buffer (SLB), 189
Segment registers, 184, 192
defined, 184
role of, 192
Segment table, 185
defined, 185
single-level store and, 192
Segmented memory, 105–106
Segment-relative addressing, 185, 192
Selection operation, 124
Semaphore, 233
Semiconductor disks, 338
Send/receive counter (SRC), 233–234
Send/receive message (SRM), 233
Serial Link Internet Protocol (SLIP), 174, 290
Serial Storage Architecture (SSA), 318
Servers
CC-NUMA, 333
database, 118–119
defined, 118
integrated PC, 305–308
Service programs, 70
SGI/Cray Origin 2000, 334–335, 347
Shared folders, 96
Shared memory systems, 46
Shared-nothing design, 43
Silverlake project, xxvii, 370–372, 376, 377
Simple Mail Transfer Protocol (SMTP), 288
Simple network management protocol (SNMP), 292
Simple-COMA (S-COMA), 335–336
Simplified client/server computing, 296–299
Single Unix Specification, 9
Single-level store, 179–224
address translation, 206–220
beginning of, 356
defined, 181
disadvantage of, 183
disk management, 220–224
objects in, 188
overview, 186–191
performance implications, 191–195
persistence, 184
process-switching performance and, 195
segment table and, 192
segment-relative addressing vs., 185–186
segments, 186
virtual memory and, 180–186
Skunkworks, 59
Slack, Keith, 365–366, 373–374
SLIC, 53–62
commitment control in, 147
cost of, 56–57
database size support, 142
defined, 53
development environment, 55–56
exception management, 246–248
exception-handling routines, 246
functions, 57
journaling, 147
kernel technologies, 57–58
main storage management component, 189
tag instructions, 198
Sloan, Jim, 124
Small Computer System Interface (SCSI), 262, 318
SNDPGMMSG (Send Program Message) command, 234
Snooping, 46, 333
Software
application, 5
design, 5–8
future technologies, 338–343
optimizing with assembler, 5
performance improvement, 6
PowerPC, 33
system, 5
Solie, Darryl, 25
Soltis, Steven, 341
Source Sink Request (SSR), 274–275
Space pointer, 76, 102
Spaces, 76
SPARC microprocessor, 20
Spatial locality, 41–42
SPD bus, 260, 261, 263, 267–270, 340
adapters, 264, 267
BCU, 268–269
connection parts, 269
I/O cards, 267
I/O hardware connections, 268
I/O structure, 272
IOBUs, 268
operations, 268–270
V4R1 support, 266
SPEC1170, 9
SPEC, 344
Special authorities, 166
“Speed Demons,” 31
Stall cycles, 42
Standard Performance Evaluation Corporation. See SPEC
State information, 225
Static directory, 223
Static storage area, 238
Static storage segments, 243
Stewart, Bob, 354–355
Storage pool, 253
Storage segments, 221–224
access group segments, 222–223
auxiliary storage directories, 223–224
disk extents, 221–222
Stored procedures, 138
Structured Query Language (SQL), 125
CALL statement, 138
collections, 130
CONNECT statement, 140, 272, 274
CREATE TABLE statement, 128
CREATE VIEW statement, 129
Development Kit, 126
FETCH statement, 272, 281, 282, 283
Interactive, 126
statements, 125
views, 129
Subdirectories, 97
Subsystems, 252–253
defined, 252
description, 252
future I/O technology, 336–337
storage, 337
Sun Ultra Enterprise server, 346
Superior, 378
Superscalar machines, 20
SuperSparc processors, 312–313
Supervisor Call (SVC) interface, 60
Suspend state, 230
Symbol computer, 354–355
Symbol Programming Language (SPL), 359
Symmetric multiprocessing (SMP), 37, 235–236
bottleneck, 312
defined, 235
designs, 44
efficiency, improving, 46
nodes, 45
parallel database support, 119
See also Asymmetric multiprocessing
Synchronous data link communications (SDLC) protocol, 275
System Application Architecture (SAA), 377
System Area Network (SAN), 46, 264–266, 336
bus, 266
interconnections, 264
loop, 268
SCIL support, 266
uses, 266
System Licensed Internal Code. See SLIC
System Object Model (SOM), 256, 301
Distributed (DSOM), 302
objects, 302, 303
System objects, 76, 77, 91, 101–104, 105–114
attributes, 111
characteristics, 103–104
commit block, 147
creation, 108
customized header, 107
damage, 112
EPA header, 107
examples, 113–114
functional portion, 101, 102
illustrated, 102
inside, 105–114
internal structure, 101
journal ports, 147
journal spaces, 147
list of, 93
object persistence, 104
permanent, 104
pointing, 102
process, 237–244
segment header, 106–107
space portion, 101
structure, 106–107
temporary, 104
See also Objects
System operator, 164
System pointers, 76, 99
resolving, 100–101
in system state, 100
unresolved, 101
System programmer, 164
System security levels, 158–163
level 10-no security, 159–160
level 20-password security, 160
level 30-resource security, 160–161
level 40-operating system security, 162
level 50-C2 level security, 163
See also Security
System software, 5
System state, 100, 162
System Support Program (SSP), 60, 62
System values, 159
System/3, 59
announcement, 359
code name, 359
integrity problems, 90
Model 2, 368
processor design, 357
System/32, 59–60, 360
System/34, 123, 360
System/36, 58–62
authority, 168
CSP, 262
office system, 96
operating system on RISC hardware, 58–59
parts, 60
processors, 11
skunkworks, 59
System/38, 32, 89
48-bit address, 179, 183
channel, 262
code name, 311–312
database integration, 116, 122–123
development, 364–366
kernel, 52
microcode, 52
object model, 89
segments, 196
tag bits, 199
tasking structure patent, 226
virtual address, 200
System/360, 356–357
instructions, 18
System 360/91, 18–19
System/370, 361–363
announcement of, 361
channels, 262
FS compatibility with, 362
System/390 Parallel Sysplex, 315
System/Q, 364–365
System/R, 124–125
System-Managed Access Path Protection (SMAPP), 134
System-wide catalog, 130

T

Tables
creating, 128
object definition (ODT), 80–81, 105
page, 192, 213
segment, 185, 192
Tag bits, 31–32, 198
setting, 198
System/38, 199
use of, 198–199
Tags, 195–206
instructions, 198
on disk, 199–200
pointer counterfeiting and, 199
System/38, 200
Tags-active mode, 32, 198–199
Tags-inactive mode, 211
Tashjian, Harry, xxx–xxxi, 352, 357, 360, 364
Task dispatching, 229–234
multiprocessor support, 234–235
send/receive queues, 233–234
Task dispatching elements (TDEs), 229, 231
address fields, 231
migration, 234
movement in system, 231
multiprocessor fields, 236
on TDQ, 232
Task dispatching queues (TDQs), 231–232
illustrated, 232
implementation, 231
multiple, 236
Tasking structure, 226–237
implementation of, 227
microkernel technologies, 226–228
patent, 226
Tasks
defined, 228
state transitions, 230–231
states of, 230
Taylor, Perry, 124–125
TCP/IP, 174
Connectivity Utilities, 288
File Transfer Protocol (FTP), 175, 176, 290
Technology-Independent Machine Interface. See MI
Temporal locality, 42
Temporary directory, 223
Temporary objects, 104
Third Level Exception Handler (TLEH), 248
Threads
application enablers for, 256
defined, 251
destroying, 256
multiple, 324
POSIX, 255
Timesharing, 181–183
defined, 181
virtual memory for, 181–183
Timing sequence, 17
Tomashek, Mike, 27–28, 53–54
Tomasulo, Bob, 19, 362
Tomasulo algorithm, 19, 20, 362
Tombstone segments, 242–243
Total cost of ownership (TCO), 292
TPC, 344–345
benchmark definition, 344
TPC-C, 344–345, 346
TPC-D, 345
See also Benchmark programs
Transaction Processing Performance Council. See TPC
Transformation tools, 118
Translation lookaside buffer (TLB), 189
holding PTEs, 217
registers, 189, 193
searching, 217
size of, 218
Translator, 67
ILE, 69
optimizing (OX), 69
Transmission Control Protocol/Internet Protocol. See TCP/IP
Triggers, 135–136
adding, 136
defined, 135
in physical files, 135–136
removing, 136
Trojan horses, 173–174
Turner, Rick, 192, 226

U

U-code, 69
Unicode format, 97
implementation of, 138
support, 99
Uniform memory access (UMA) machines, 43, 331
Unix
advantages of, 348
file system, 97, 98
layered approach, 226–227
subsystems, 227
thread support, 301
User class, 163, 164
authorities, 163
list of, 164
User interfaces, 341–342
User profiles, 163–166
authorization of objects, 163, 165–166
capability definition, 163–164
defined, 77, 163
objects owned and authorized, 163, 165
privileged instructions, 163–164, 166
QTMHHTTP, 175
special authorities, 163–164, 166
user class, 163, 164
User state, 162

V

Van Benschoten, Glenn, 10
VAX systems, 314, 348
Version 3, xxxiv, 285
Version 4
application enablement, 299–309
client/server computing, 296–299
collaborative computing, 294–296
data capabilities, 310–311
enhancements, 285–287
high-end growth, 311–316
introduction, xxxiv
network computing, 287–294
price/performance improvements, 316–319
Vertical Licensed Internal Code (VLIC), 53
components, 55
programmers, 56
programming language, 55
Vertical Microcode (VMC), 52, 202–203
Very Long Instruction Word (VLIW), 325
compiler, 326
core, 331
functional units, 327
history of, 328–331
instructions, 327, 328
name of, 327
parallel dispatching, 328
performance advantage, 326
PowerPC-compatible, 330
problem with, 327
processor, 326–327
in Rochester, 328–331
technology, 325
work holdup, 330–331
Views
categories of, 128–129
creating, 128–129
SQL, 129
Virtual address, 206
System/38, 200
translation, 206–220
Virtual memory, 105, 180–186
beginnings of, 180–181
early implementation, 184
garbage collection problem, 184
persistent, 184–186
single-level, 183–184
for timesharing, 181–183
two-level, 183
See also Memory
Virtual page number (VPN), 211
abbreviated (AVPN), 215
bits, 215
as index, 213
matching, 216
one-to-one mapping of, 213
size, 213
See also Real page number (RPN)
Virtual segment identifier (VSID), 210–211
Virtual-to-real address translation, 213–220
hashing, 213–215
memory access modes, 218–219
page protection, 219–220
page table entry, 215–218
See also Address translation
Viruses, 172–173
VisualAge for Java, 303
VR2000 computer, 348–349

W

Wait state, 230
Watson, H. Mitchell, 371
W-code, 79
Web serving security, 174–176
Wells Department Store, 367–368
Wilson, Larry, 357, 359
Windows NT
application processor, 307
design team, xxiii
hardware independence and, 308
memory management component, 192
NT file system (NTFS), 308
thread support, 301
Work management, 251–254
concepts, 251–252
illustrated, 252
job structures, 253–254
subsystems, 252–253
Workflow, 295
Workplace, 374–376
Workstation user, 164
World Wide Web, 288
Worms, 173
Worttreng, Andy, 24
WRKSYSSTS (Work with System Status) command, 231

Z

Zeitler, Bill, xxxiii
Zingg, Roy, 355


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