
7 IPL levels: 1 to 7.

the current priority level is indicated in SR bits.

An interrupt request is signalled by asserting an interrupt
priority on the IPL0 to IPL2 input lines. An interrupt will
occur after the current instruction processing if:
- this IRQ priority is greater than the current IPOL mask in SR
or 
- the IRQ priority is 7 and IRQ level 7 is not already pending.

otherwise, the IRQ priority is made pending, waiting until the 
IPL mask in SR goes below this IRQ priority.


